Back to results
US 8,015,428 B2Granted
Processing device and clock control method
AssigneeRenesas Electronics Corporation
InventorsYoshinori Mochizuki, Masaharu Ukeda, Shigemasa Shiota
Life of this patent
Estimating the term…
Abstract
A processing device comprises an interface and its control circuit for performing data transfer in synchronization with an external clock, an internal oscillator, and an interface and its control circuit for performing data transfer by using an internal clock generated by the internal oscillator. In the processing device, a clock control circuit that switches a system clock between the internal clock and the external clock in accordance with the interface is provided. When the system clock is switched, the switching is performed after the CPU is set in a sleep state, and after the switching is completed, the sleep state of the CPU is released to restart the operation.
Claims11
A processing device, comprising:
- a CPU;
- a first interface for performing data transfer with an external terminal device in synchronization with an external clock supplied from the external terminal device;
- a first control circuit for the first interface;
- a clock generation circuit that generates a clock;
- a second interface for performing data transfer with the external terminal device by using an internal clock generated by the clock generation circuit;
- a second control circuit for the second interface;
- and
- a clock control circuit that switches a system clock used by at least the CPU in the processing device between the external clock and the internal clock in accordance with either one of the first and second interfaces used by the processing device in data transfer with the external terminal device,
- wherein, when the system clock is switched between the external clock and the internal clock, the processing device causes the CPU to be in a sleep state and performs the switching by the clock control circuit, and after the switching is completed, the processing device releases the sleep state of the CPU to restart an operation, and
- an external terminal complying with ISO 7816-2, wherein the first interface is an interface for performing data transfer complying with ISO 7816-3, and the second interface is an interface for performing USB transfer complying with ISO 7816-12.
7 more elements
A processing device, comprising:
- a CPU;
- an interface for performing data transfer with an external terminal device in synchronization with an external clock supplied from the external terminal device;
- a control circuit that controls the data transfer;
- a clock generation circuit that generates a clock;
- and
- a clock control circuit that switches a system clock used by at least the CPU in the processing device by a command transmitted from the external terminal device between the external clock and an internal clock generated by the clock generation circuit,
- wherein, when the system clock is switched between the external clock and the internal clock, the processing device causes the CPU to be in a sleep state and performs the switching by the clock control circuit, and after the switching is completed, the processing device releases the sleep state of the CPU to restart an operation, and
- an external terminal complying with ISO 7816-2, wherein the interface is an interface for performing data transfer complying with ISO 7816-3.
5 more elements
A processing device, comprising:
- a CPU;
- a first interface for performing data transfer with an external terminal device in synchronization with an external clock supplied from the external terminal device;
- a control circuit for the first interface;
- a first clock generation circuit that generates a clock;
- a second interface for performing data transfer with the external terminal device by using a first internal clock generated by the first clock generation circuit;
- a control circuit for the second interface;
- a second clock generation circuit that generates a clock;
- a third interface for performing data transfer with the external terminal device by using a second internal clock generated by the second clock generation circuit;
- a control circuit for the third interface;
- and
- a clock control circuit that switches a system clock used by at least the CPU in the processing device among the external clock, the first internal clock and the second internal clock in accordance with any one of the first, second and third interfaces used by the processing device in data transfer with the external terminal device,
- wherein, when the system clock is switched among the external clock, the first internal clock and the second internal clock, the processing device causes the CPU to be in a sleep state and performs the switching by the clock control circuit, and after the switching is completed, the processing device releases the sleep state of the CPU to restart an operation, and
- an external terminal complying with ISO 7816-2, wherein the first interface is an interface for performing data transfer complying with ISO 7816-3, the second interface is an interface for performing USB transfer complying with ISO 7816-12, and the third interface is an interface for performing data transfer with an RF circuit in the external terminal device.
10 more elements
Dependencies are inferred from the claim text.