System and method for prioritization of clock rates in a multi-core processor

A system for adjusting power consumed by a multi-core processor, comprising:

• a plurality of cores of the processor;
• means for measuring an instruction arrival rate for each of the plurality of cores for a time period, the instruction arrival rate determined for a particular core of the plurality of cores by measuring a number of instructions arriving at the particular core for processing by the particular core during the time period;
• means for assigning a maximum permissible power usage by the processor;
• means for calculating an optimal instruction arrival rate for each core of the plurality of cores, the optimal instruction arrival rate for the each core selected in response to the core measured instruction arrival rate for all cores of the plurality of cores and selected to limit a total power used by the processor to be less than the maximum permissible power usage of the processor, so that a sum of power used by all cores of the plurality of cores is less than the maximum permissible power usage of the processor;
• and
• means for setting the each core of the plurality of cores to the calculated optimal instruction arrival rate for a next time period.

A system for adjusting power consumed by a multi-core processor, comprising:

• a processor having a plurality of cores;
• a maximum permissible power usage by the processor;
• the processor configured to,
• (i) measure an instruction arrival rate for each of the plurality of cores for a time period, the instruction arrival rate determined for a particular core of the plurality of cores by measuring a number of instructions arriving at the particular core for processing by the particular core during the time period;
• (ii) calculate an optimal instruction arrival rate for each core of the plurality of cores, the optimal instruction arrival rate for the each core selected in response to the core measured instruction arrival rate for all cores of the plurality of cores and selected to limit a total power used by the processor to be less than the maximum permissible power usage of the processor, so that a sum of power used by all cores of the plurality of cores is less than the maximum permissible power usage of the processor;
• and
• (iii) set the each core of the plurality of cores to the calculated optimal instruction arrival rate for the each core for a next time period.

A system to adjust power consumed by a multi-core processor, comprising:

• a processor having a plurality of cores;
• a maximum permissible power usage by the processor;
• the processor configured to connect with a monitoring module, the monitoring module configured to
• (i) measure an instruction arrival rate for each of the plurality of cores associated therewith for a time period, the instruction arrival rate determined for a particular core of the plurality of cores by measuring a number of instructions arriving at the particular core for processing by the particular core during the time period;
• (ii) calculate an optimal instruction arrival rate for each core of the plurality of cores, the optimal instruction arrival rate for the each core selected in response to the core measured instruction arrival rate for all cores of the plurality of cores and selected to limit a total power used by the processor to be less than the maximum permissible power usage of the processor, and
• (iii) set the each core of the plurality of cores to the calculated optimal instruction arrival rate for the each core for a next time period.

A physical computer-readable storage media containing executable program instructions for execution by a processor, the physical computer-readable storage media comprising:

• program instructions that measure an instruction arrival rate for each of a plurality of cores of a processor for a time period, the instruction arrival rate determined for a particular core of the plurality of cores by measuring a number of instructions arriving at the particular core for processing by the particular core during the time period;
• program instructions that assign a maximum permissible power usage by the processor;
• program instructions that calculate an optimal instruction arrival rate for each core of the plurality of cores, the optimal instruction arrival rate for the each core selected in response to the core measured instruction arrival rate for all cores of the plurality of cores and selected to limit a total power used by the processor to be less than the maximum permissible power usage of the processor, so that a sum of power used by all cores of the plurality of cores is less than the maximum permissible power usage of the processor;
• and
• program instructions that sett the each core of the plurality of cores to the calculated optimal instruction arrival rate for the each core for a next time period.