Updating instructions to free core in multi-core processor with core sequence table indicating linking of thread sequences for processing queued packets

A method of updating execution instructions of a multi-core processor, comprising:

• an iterative process of:
• freeing one programmable processing core of a set of multiple programmable processing cores integrated on a single die from packet processing operations;
• replacing an existing execution instructions of the one programmable processing core with new execution instructions while at least one of the other programmable processing cores continues to process received packets;
• maintaining data identifying a core sequence, wherein the freeing one programmable processing core comprises removing the core from the core sequence before the updating;
• and
• inserting the core into the core sequence after the updating;
• whereby a sequence of threads provided by the cores can sequentially retrieve packets to process from at least one queue, the sequence proceeding from a subsequence of at least one thread of one core to a subsequence of at least one thread on another core;
• and
• wherein the sequence of threads is specified by the data identifying the core sequence.

A computer program product for updating execution instructions of a multi-core processor, said program disposed on a computer readable medium and including instructions for causing a processor to perform operations comprising:

• receiving Internet Protocol packets at a processor including multiple programmable processing cores integrated on a single die;
• selecting a first subset of at least one of the programmable processing cores;
• and
• loading at least a portion of the execution instructions to the first subset of programmable processing cores and replacing existing execution instructions, associated with the first subset of programmable processing cores, with the received execution instructions while at least one of the programmable processing cores not in the first subset continues to process received packets;
• wherein a sequence of threads provided by the cores sequentially retrieve packets to process from at least one queue, the sequence proceeding from a subsequence of at least one thread of one core to a subsequence of at least one thread on another core;
• and
• wherein the sequence of threads is specified by data identifying, at least, the next core in the sequence.

A computer program product for updating execution instructions of a multi-core processor, said program disposed on a computer readable medium and including instructions for causing a processor to perform operations comprising an iterative process of:

• freeing one programmable processing core of a set of multiple programmable processing cores integrated on a single die from packet processing operations;
• replacing an existing execution instructions of the one programmable processing core with new execution instructions while at least one of the other programmable processing cores continues to process received packets;
• maintaining data identifying a core sequence, wherein the freeing one programmable processing core comprises removing the core from the core sequence before the updating;
• and
• inserting the core into the core sequence after the updating;
• whereby a sequence of threads provided by the cores can sequentially retrieve packets to process from at least one queue, the sequence proceeding from a subsequence of at least one thread of one core to a subsequence of at least one thread on another core;
• and
• wherein the sequence of threads is specified by the data identifying the core sequence.