Simultaneous multiple thread processor increasing number of instructions issued for thread detected to be processing loop
AssigneePanasonic Corporation
InventorTakenobu Tani
Life of this patent
Estimating the term…
Abstract
A processor simultaneously issues instructions to multiple threads in a same instruction execution cycle. An instruction issuer controls issuance of an instruction for each of the multiple threads. A detector detects, for each of the multiple threads, whether a loop processing is currently being executed. A unit causes the instruction issuer to increase a number of instructions to be issued when the detector detects that the loop processing is currently being executed.
Claims17
A processor which simultaneously issues instructions to multiple threads in a same instruction execution cycle, comprising:
- an instruction issuer that controls issuance of the instructions to each of the multiple threads;
- and
- a detector that detects, for each of the multiple threads, whether a loop process is currently being executed,
- wherein said instruction issuer increases a number of the instructions to be issued to one of the multiple threads when said detector detects that the loop process is currently being executed by the one of the multiple threads.
A processor which simultaneously issues instructions to multiple threads in a same instruction execution cycle, comprising:
- an instruction issuer that controls issuance of the instructions to each of the multiple threads;
- and
- a detector that detects, for each of the multiple threads, whether a loop process is currently being executed,
- wherein said instruction issuer is requested to increase a number of the instructions to be issued to one of the multiple threads when said detector detects that the loop process is currently being executed by the one of the multiple threads.
Dependencies are inferred from the claim text.