US 8,015,389 B2 · Memory device, memory controller and memory system

Abstract

An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.

Claims4

Dependent claims

A semiconductor integrated circuit in which circuits are integrated on a single semiconductor substrate, the semiconductor integrated circuit comprising:

a memory array in which memory cells connected to word lines and bit lines and storing data are arranged in the form of a matrix, and the memory array being sectioned into a plurality of bit groups, each of the plurality of bit groups having Nb number of memory cells, and each of the bit group storing Nb bits;
a controller that selects a plurality of bit groups on the basis of an address signal including a row address signal and a column address signal, and further selects a bit group as a starting point among the selected plurality of bit groups, on the basis of a first combination information indicating a start position in the selected plurality of bit groups;
and
Nb×N number of output terminals,
wherein the controller outputting, from the Nb×N number of output terminals in parallel, on the basis of a second combination information, data items that are stored in the memory cells contained in N number of bit groups including the bit group at the starting point.

2 more elements

Dependencies are inferred from the claim text.

Memory device, memory controller and memory system

Life of this patent

Memory device, memory controller and memory system

Life of this patent

Abstract

Claims4