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US 8,015,372 B2Granted
Apparatus and method for memory migration in a distributed memory multiprocessor system
AssigneeNEC Corporation
InventorTakeo Hosomi
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AssigneeNEC Corporation
InventorTakeo Hosomi
Estimating the term…
A distributed memory multiprocessor system including a plurality of cells interconnected via an inter-cell network, each of the plurality of cells including at least one cache, a memory, a memory controller, and a directory managing a status of data stored in the memory, the distributed memory multiprocessor system includes a directory information updating unit of a first cell that updates the directory of the first cell, and a directory information transmitting unit of a second cell that transmits the directory information contained in the directory of the second cell. The directory information transmitting unit of the second cell transmits the directory information, which is read out from the directory of the second cell, to the first cell. And, the directory information updating unit of the first cell receives the directory information transmitted by the directory information transmitting unit of the second cell and updates the directory of the first cell.
A distributed memory multiprocessor system including a plurality of cells interconnected via an inter-cell network, each of the plurality of cells including at least one cache, a memory, a memory controller, and a directory managing a status of data stored in the memory, the distributed memory multiprocessor system comprising:
A memory controlling apparatus, included in a cell that is connected with at least one other cell, the memory controlling apparatus comprising:
A memory controlling apparatus, included in a cell that is connected with at least one other cell, the memory controlling apparatus comprising:
A memory migration method in a distributed multiprocessor system including a plurality of cells interconnected via an inter-cell network, each of the plurality of cells including one or more caches, a memory, a memory controller, and a directory managing the status of data stored in the memory, the memory migration method comprising:
A computer readable tangible memory containing a program of instructions for enabling a computer, serving as a memory controlling apparatus included in a cell that is connected with at least one other cell, to execute processes, comprising:
A computer readable tangible memory containing a program of instructions for enabling a computer, serving as a memory controlling apparatus included in a cell that is connected with at least one other cell, to execute processes, comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Cache consistency protocols: using directory methods
Performance improvement: hit rate improvement
Computing and data processing
About 3 years 3 months of term left · ends 14 Jan 2030 (estimated)
This application is based upon and claims priority from Japanese patent application No. 2008-26381, filed on Feb. 6, 2008 in the Japanese Patent Office, the disclosure of which is incorporated herein its entirely by reference.
1. Field of the Invention
The present invention relates to an apparatus and method for memory migration in a distributed memory multiprocessor system.
Aspects of embodiments of the present invention will become more apparent by describing in detail embodiments thereof with reference to the accompanying drawings, in which:
FIG. 1 is a diagram showing a configuration of a distributed memory multiprocessor system according to first and second embodiments,
FIG. 2 is a diagram showing a configuration of a memory controller 152 of a new cell 112 according to the first embodiment.
A first embodiment of the present invention will be described in detail with reference to the drawings.
FIG. 1 shows a configuration of a distributed multiprocessor system of the present invention.
The system includes four cells 110, 112, 114, 116, which are interconnected through inter-cell networks 180, 182. The cell 110 includes two processors 120A, 120B, which are connected to caches 130A, 130B, respectively. The cell 110 further includes a memory controller 150 connecting to a memory 160 and a directory 170. An intra-cell network 140 interconnects the caches 130A, 130B, the memory controller 150, and the inter-cell network 180.