Processor extensions for accelerating spectral band replication
AssigneeSiPort, Inc.
InventorsSridhar Sharma, Binuraj Ravindran, Jeffrey V. Hill
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Abstract
Enhancements to hardware architectures (e.g., a RISC processor or a DSP processor) to accelerate spectral band replication (SBR) processing are described. In some embodiments, instruction extensions configure a reconfigurable processor to accelerat SBR and other audio processing. In addition to the instruction extensions, execution units (e.g., multiplication and accumulation units (MACs)) may operate in parallel to reduce the number of audio processing cycles. Performance may be further enhanced through the use of source and destination units which are configured to work with the execution units and quickly fetch and store source and destination operands.
Claims32
A system for accelerating audio processing, the system comprising:
- a reconfigurable core processor that processes audio data received from system memory, and wherein the reconfigurable core processor is communicatively coupled to a register file and an auxiliary register file;
- a plurality of hardware accelerators, including multiply-accumulate (MAC) units executable to perform operations for accelerating the processing of audio data, the plurality of MAC units:
- coupled to the register file and the auxiliary register file, and
- sharing registers in each of the register file and the auxiliary register file with the reconfigurable core processor, and wherein the shared registers allow for parallel processing of audio data by the MAC units and the reconfigurable core processor;
- a source control unit that fetches operands for at least one of the plurality of MAC units from the shared registers;
- and
- a destination control unit that stores values derived by at least one of the MAC units in the shared registers, and wherein the derived values may be used to reconfigure an audio processing operation of the core processor.
A system for accelerating the processing of audio data, the system comprising:
- a first memory storing a history buffer and a first plurality of finite impulse response filter coefficients;
- a plurality of execution units configured to execute in parallel, each of the plurality of execution units multiplying a first value from the history buffer and at least one finite impulse response filter coefficient from the first plurality of finite impulse response filter coefficients to generate a first result for performing QMF analysis;
- a second memory that stores the first result;
- and
- a reconfigurable processor that:
- receives the first result from the second memory,
- receives an instruction extension for performing a discrete cosine transform on the first result, and
- performs the discrete cosine transform on the first result in accordance with the execution of the instruction extension.
A method for performing QMF analysis, the method comprising:
- receiving a first and a second time domain audio sample;
- retrieving a plurality of finite impulse response filter coefficients from memory;
- executing a hardware accelerators, including at least one multiply-accumulate (MAC) unit to multiply-accumulate the first time domain audio sample with a first finite impulse response filter coefficient of the plurality of finite impulse response filter coefficients and multiplying the second time domain audio sample with a second finite impulse response filter coefficient of the plurality of finite impulse response filter coefficients to generate a real result, wherein the multiply-accumulating of the first time domain and the multiplying of the second time domain occurs in parallel;
- and
- performing a discrete cosine analysis to output a real sub-band, the analysis occurring in accordance with execution of an instruction extension stored in memory and executed by a processor.
A system for accelerating audio processing, the system comprising:
- a reconfigurable processor that processes audio data;
- a hardware extension block to assist the reconfigurable processor in accelerating processing of audio data, the hardware extension block containing:
- a first execution unit that executes custom processing, including multiply-accumulate operations related to the processing of audio data,
- a second execution unit that performs custom processing, including multiply-accumulate operations in parallel with the first execution unit;
- a source control unit that fetches operands for at least one of the first or second execution units;
- and
- a destination control unit that stores values from at least one of the execution units.
A system for accelerating audio processing, the system comprising:
- a general purpose RISC processor;
- an audio co-processor communicatively coupled to the general purpose processor via shared register files and memory, wherein both processors processes audio data received from system memory, and wherein the audio co-processor includes a plurality of hardware accelerators including multiply-accumulate (MAC) units that are executable to perform operations for accelerating the processing of audio data, the plurality of MAC units:
- coupled to the register file and the auxiliary register file, and
- sharing registers in each of the register file and the auxiliary register file with the general purpose RISC processor, wherein the shared registers allow for parallel processing of audio data by the MAC units and the audio co-processor, the processed audio data shared with the general purpose RISC processor.
Dependencies are inferred from the claim text.