Back to results
US 8,015,365 B2Granted
Reducing back invalidation transactions from a snoop filter
AssigneeIntel Corporation
InventorsTsvika Kurts, Kai Cheng, Jeffrey D. Gilbert, Julius Mandelblat
Life of this patent
Estimating the term…
Abstract
In one embodiment, the present invention includes a method for receiving an indication of a pending capacity eviction from a caching agent, determining whether an invalidating writeback transaction from the caching agent is likely for a cache line associated with the pending capacity eviction, and if so moving a snoop filter entry associated with the cache line from a snoop filter to a staging area. Other embodiments are described and claimed.
Claims20
A method comprising:
- receiving an indication of a pending capacity eviction from a caching agent in a coherency controller, the pending capacity eviction corresponding to a read transaction that indicates that a cache line associated with the pending capacity eviction is to be evicted to provide space for results of the read transaction;
- determining in the coherency controller whether an invalidating writeback transaction from the caching agent is likely to be sent from the caching agent to the coherency controller for the cache line associated with the pending capacity eviction;
- and
- if the invalidating writeback transaction is likely, moving a snoop filter entry associated with the cache line from a snoop filter of the coherency controller to a staging area of the coherency controller.
1 more element
An apparatus comprising:
- a snoop filter to store entries each associated with a cache line of a cache memory, wherein the snoop filter is inclusive with a plurality of cache memories;
- and
- a coherency unit coupled to the snoop filter to control the snoop filter, wherein the coherency unit is to withhold transmission of a back invalidation transaction for a snoop filter entry to be evicted from the snoop filter responsive to a pending capacity eviction from the cache memory if the cache memory is likely to send an invalidation transaction to the coherency unit for a cache line corresponding to the evicted snoop filter entry.
A system comprising:
- a first processor including at least one core and at least one cache memory;
- a second processor including at least one core and at least one cache memory;
- a chipset coupled to the first and second processors, the chipset including a snoop filter to store entries each associated with a cache line of one of the cache memories, a coherency unit coupled to the snoop filter to withhold transmission of a back invalidation transaction for a snoop filter entry to be evicted from the snoop filter responsive to a pending capacity eviction from one of the first and second processors if the first or second processor is likely to send an invalidation transaction to the coherency unit for a cache line corresponding to the evicted snoop filter entry, and a storage area coupled to the snoop filter to store snoop filter entries evicted from the snoop filter and before a back invalidation transaction is sent from the coherency unit;
- and
- a dynamic random access memory (DRAM) coupled to the chipset.
2 more elements
Dependencies are inferred from the claim text.