Method and system for handling cache coherency for self-modifying code

A system for handling cache coherency for self-modifying code, comprising:

• program store compare (PSC) components for execution by a processor, the PSC components including a load store unit (LSU), an instruction cache, and a coherency logic, the PSC components configured to perform a method, comprising:
• allocating a program store compare (PSC) tag by the LSU in response to determining a cache line is not exclusive in a data cache for a store operation;
• sending the PSC tag with an exclusive fetch for the cache line to the coherency logic;
• sending a cache invalidation request that includes an address to be invalidated, the PSC tag, and an indicator specifying the request is for a PSC operation;
• receiving at the instruction cache the cache invalidation request and comparing the requested address with an address table that stores addresses of pending instructions fetched by a processor, the instruction cache bypassing a cache invalidation state machine for a duration of the comparison;
• and
• sending an indicator of a match and the PSC tag, by the instruction cache, to the LSU, responsive to a match resulting from the comparison the indicator of the match sent within a first period of time after the cache invalidation request, the LSU processing the match indication;
• wherein the LSU discards prefetched instructions following execution of the store operation that stores to a cache line, subject to an exclusive data return for which the match is indicated, within a time period no greater than the total of the first period of time from the cache invalidate request to the match indication, and a second period of time from the cache invalidation request to an exclusive data return to the LSU.