US 8,015,358 B2 · System bus structure for large L2 cache array topology with different latency domains

Abstract

A cache memory which loads two memory values into two cache lines by receiving separate portions of a first requested memory value from a first data bus over a first time span of successive clock cycles and receiving separate portions of a second requested memory value from a second data bus over a second time span of successive clock cycles which overlaps with the first time span. In the illustrative embodiment a first input line is used for loading both a first byte array of the first cache line and a first byte array of the second cache line, a second input line is used for loading both a second byte array of the first cache line and a second byte array of the second cache line, and the transmission of the separate portions of the first and second memory values is interleaved between the first and second data busses.

Claims15

Dependent claims

A method of operating a cache memory, comprising:

determining that the cache memory does not have currently valid entries corresponding to first and second requested memory values;
and
loading the first and second requested memory values respectively into first and second cache lines of the cache memory by receiving separate portions of the first requested memory value from a first data bus over a first time span of successive clock cycles and receiving separate portions of the second requested memory value from a second data bus over a second time span of successive clock cycles, wherein the first time span at least partially overlaps with the second time span.

A computer system comprising:

one or more processors which process program instructions;
a memory device;
and
a cache memory connected to said one or more processors and said memory device to temporarily store values that are used by said one or more processors, said cache memory including
a cache array having a plurality of cache lines,
a cache directory which determines that the cache array does not have currently valid entries corresponding to first and second memory values requested from said one or more processors,
a first data bus that receives separate portions of the first requested memory value over a first time span of successive clock cycles,
a second data bus that receives separate portions of the second requested memory value over a second time span of successive clock cycles, wherein the first time span at least partially overlaps with the second time span, and
a cache controller that identifies which portions of the first and second requested memory values are being received and loads the first and second requested memory values respectively into first and second cache lines of said cache array.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application

12/207,393Filed 9 Sep 2008 · continuation

Priority

10 Feb 2005

Published

US 2009/0006758 A11 Jan 2009

Granted

6 Sep 2011

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 12/0811
Multiuser, multiprocessor or multiprocessing cache systems: with multilevel cache hierarchies
G06F 12/0851
Cache with multiple tag or data arrays being simultaneously accessible: cache with interleaved addressing
G06F 12/1045
Using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]: associated with a data cache
G06F 12/0831
Cache consistency protocols: using a bus scheme, e.g. with bus monitoring or watching means

Family

Application11/054,925Parent of this continuation · filed 10 Feb 2005

US 2009/0006758 A1Pre-grant publication · published 1 Jan 2009

US 7,469,318 B2Parent of this continuation

US 2006/0179222 A1Published application

US 8,015,358 B2This patent

From the US filing history. Foreign family members aren’t listed.

System bus structure for large L2 cache array topology with different latency domains

Life of this patent

System bus structure for large L2 cache array topology with different latency domains

Life of this patent

Abstract

Claims15