Memory address management systems in a large capacity multi-level cell (MLC) based flash memory device

A system for managing memory address of a multi-level cell (MLC) based flash memory device comprising:

• an input/output interface circuit, coupling to a processing unit, configured for receiving a logical sector address (LSA) along with a data transfer request from a host computing device, said processing unit is configured for extracting set, entry, page and sector numbers from the LSA using an indexing scheme, said processing unit further comprising a page buffer, an address correlation page usage memory (ACPUM), a partial logical-to-physical address and page usage information (PLTPPUI) tracking table, a wear leveling counter and bad block indicator (WL/BB) tracking table;
• and
• a flash memory that includes a reserved area for a plurality of first physical blocks and a plurality of second physical blocks, the first physical blocks being referenced by a plurality of respective first special logical addresses and the second physical blocks by a plurality of respective second special logical addresses;
• wherein the first physical blocks are configured for storing PLTPPUI and the second physical blocks for storing wear leveling and bad block (WL/BB) indicator, said ACPUM is configured to keep one set, corresponding to the set number, of PLTPPUI, the PLTPPUI tracking table is configured to hold a correlation between the first special logical addresses and the first physical blocks and the WL/BB tracking table is configured to hold a correlation between the second special logical addresses and the second physical blocks.