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US 8,015,326 B2Granted
Central processing apparatus, control method therefor and information processing system
AssigneeFujitsu Limited
InventorsHideyuki Unno, Masaki Ukai
Life of this patent
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AssigneeFujitsu Limited
InventorsHideyuki Unno, Masaki Ukai
Estimating the term…
A plurality of system controllers 300 each comprising a memory medium 400 and an I/O device 500 under the control of the system controller 300 are connected to a CPU node 100 by way of a plurality of system buses 200. The CPU node 100 executes a memory interleave for distributing memory accesses to the system buses 200 (i.e., the system controllers 300). In performing an I/O access to the I/O device 500, the CPU node 100 firstly inquires from a representative system controller 300 (SC0) as to which system bus 200 (i.e., a system controller 300) has a target I/O device 500 and then executes an actual I/O access to the system bus 200 returned in a response from the SC0. Even when the CPU node 100 executes a memory interleave in the case of a memory-mapped I/O, the CPU node 100 is not required to manage the location information of the I/O device 500.
A information processing apparatus, comprising:
A control method for an information processing apparatus including a processor connecting to a plurality of the system controllers, each connecting to one of a plurality of devices each of which stores data accessed by using an address and replies the data when accessed, the control method comprising:
Dependencies are inferred from the claim text.