US 8,015,231 B2Granted

Data processing apparatus and method for performing floating point multiplication

AssigneeArm Limited

InventorsDavid Raymond Lutz, Christopher Neal Hinds

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Abstract

A data processing apparatus and method includes multiplier logic operable to multiply the first and second n-bit significands to produce a pair of 2n-bit vectors. Half adder logic is arranged to produce a plurality of carry and sum bits representing a corresponding plurality of most significant bits of the pair of 2n-bit vectors. The first adder logic then performs a first sum operation with a first rounded result and a second adder logic performs a second sum operation with a second rounded result. The required n-bit result is then derived from either the first rounded result or the second rounded result. The data processing apparatus takes advantage of a property of the half adder form to enable a rounding increment value to be injected prior to performance of the first and second sum operations without requiring full adders to be used to inject the rounding increment value.

Claims18

Dependent claims

A data processing apparatus for multiplying first and second n-bit significands of first and second floating point operands to produce an n-bit result, the data processing apparatus comprising:

multiplier logic circuitry for multiplying the first and second n-bit significands to produce a pair of 2n-bit vectors;
half adder logic circuitry for receiving a plurality of most significant bits of the pair of 2n-bit vectors and to produce a corresponding plurality of carry and sum bits representing said plurality of most significant bits;
first adder logic circuitry for performing a first sum operation in order to generate a first rounded result equivalent to the addition of the pair of 2n-bit vectors with a rounding increment injected at a first predetermined rounding position appropriate for a non-overflow condition, the first adder logic circuitry being arranged to use as the m most significant bits of the pair of 2n-bit vectors the corresponding m carry and sum bits, and to take the remaining 2n-m least significant bits of the pair of 2n-bit vectors directly from the 2n-bit vectors, with the least significant of the m carry bits replaced with a rounding increment value prior to the first adder logic performing the first sum operation, wherein n and m are integers and 2n is greater than m;
second adder logic circuitry for performing a second sum operation in order to generate a second rounded result equivalent to the addition of the pair of 2n-bit vectors with a rounding increment injected at a second predetermined rounding position appropriate for an overflow condition, the second adder logic circuitry being arranged to use as the m−1 most significant bits of the pair of 2n-bit vectors the corresponding m−1 carry and sum bits, and to take the remaining 2n-m+1 least significant bits of the pair of 2n-bit vectors directly from the 2n-bit vectors, with the least significant of the m−1 carry bits replaced with the rounding increment value prior to the second adder logic performing the second sum operation;
and
selector logic circuitry for deriving the n-bit result from either the first rounded result or the second rounded result.

3 more elements

A method of operating a data processing apparatus to multiply first and second n-bit significands of first and second floating point operands to produce an n-bit result, the method comprising the steps of:

multiplying the first and second n-bit significands to produce a pair of 2n-bit vectors;
employing half adder logic circuitry to produce from a plurality of most significant bits of the pair of 2n-bit vectors a corresponding plurality of carry and sum bits representing said plurality of most significant bits;
performing a first sum operation in order to generate a first rounded result equivalent to the addition of the pair of 2n-bit vectors with a rounding increment injected at a first predetermined rounding position appropriate for a non-overflow condition, the first sum operation using as the m most significant bits of the pair of 2n-bit vectors the corresponding m carry and sum bits, and taking the remaining 2n-m least significant bits of the pair of 2n-bit vectors directly from the 2n-bit vectors, with the least significant of the m carry bits replaced with a rounding increment value prior to performing the first sum operation, wherein n and m are integers and 2n is greater than m;
performing a second sum operation in order to generate a second rounded result equivalent to the addition of the pair of 2n-bit vectors with a rounding increment injected at a second predetermined rounding position appropriate for an overflow condition, the second sum operation using as the m−1 most significant bits of the pair of 2n-bit vectors the corresponding m−1 carry and sum bits, and taking the remaining 2n-m+1 least significant bits of the pair of 2n-bit vectors directly from the 2n-bit vectors, with the least significant of the m−1 carry bits replaced with the rounding increment value prior to performing the second sum operation;
and
deriving the n-bit result from either the first rounded result or the second rounded result.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/999,154Filed 30 Nov 2004
Published: US 2006/0117080 A11 Jun 2006
Granted: 6 Sep 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 7/487
Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or…:…
G06F 7/49915
Overflow or underflow: mantissa overflow or underflow in handling floating-point numbers
G06F 7/49936
Denomination or exception handling, e.g. rounding or overflow: normalisation mentioned as feature only
G06F 7/49963
Rounding: rounding to nearest