Self-test circuit for high-definition multimedia interface integrated circuits

A high-definition multimedia interface circuit, comprising:

• a test pattern generator to generate a test pattern;
• a high-definition multimedia interface encoder to encode the test pattern;
• an output circuit, operatively connected to said high-definition multimedia interface encoder, to produce high frequency data from the encoded test pattern;
• a sampling circuit, capacitively connected to said output circuit, to produce sampled data corresponding to the high frequency data having a clock rate less than a clock rate of the high frequency data;
• and
• a test circuit, operatively connected to said sampling circuit, to compare the sampled data with the test pattern.

A high-definition multimedia interface circuit, comprising:

• a test pattern generator to generate a test pattern;
• a high-definition multimedia interface encoder to produce a plurality of channels of encoded data from the test pattern;
• an output circuit, operatively connected to said high-definition multimedia interface encoder, to produce a plurality of channels of high frequency data from the plurality of channels of encoded data;
• a multiplexer, operatively connected to said output circuit, to select a channel for sampling;
• a capacitive coupler, operatively connected to said multiplexer;
• a sampling circuit, operatively connected to said capacitive coupler, to produce sampled data corresponding to the high frequency data having a clock rate less than a clock rate of the high frequency data;
• and
• a test circuit, operatively connected to said sampling circuit, to compare the sampled data with the test pattern.