Distributed micro instruction set processor architecture for high-efficiency signal processing

A wireless communication system, comprising:

• a plurality of hardware planes, at least one of the hardware planes comprising:
• a plurality of finger kernels, each finger kernel including a finger application specific instruction set processor (ASISP);
• and
• a combiner kernel configured to combine outputs of the finger kernels, the combiner kernel including a combiner ASISP;
• and
• a controller configured to control a processing schedule for the plurality of hardware planes of the wireless communication system.

A wireless communication base station comprising:

• a plurality of hardware planes, at least one of the hardware planes comprising:
• a plurality of finger kernels, each finger kernel including a finger application specific instruction set processor (ASISP);
• and
• a combiner kernel configured to combine outputs of the finger kernels, the combiner kernel including a combiner ASISP;
• and
• a controller configured to control a processing schedule for the plurality of hardware planes of the wireless communication base station.

A method of allocating a hardware plane to processes supported by a wireless communication system having a hardware plane controllable by a scheduler, the method comprising:

• at a first time-slice, allocating the hardware plane to a first process;
• at a second time-slice, reallocating the hardware plane to a second process, and inactivating the first process;
• and
• at the second time-slice, retrieving from a memory state information parameters associated with the second process.

A method of allocating a hardware plane to processes supported by a wireless communication system having the hardware plane controllable by a scheduler, the hardware plane having a plurality of finger kernels with respective application specific instruction set processors (ASISPs) and a combiner kernel configured to combine outputs of the finger kernels and having a combiner ASISP and a memory, the method comprising:

• at a first time-slice, the scheduler sending a request to the hardware plane to activate a first process;
• at a second time-slice, the scheduler sending a request to the hardware plane to activate a second process, and inactivate the first process;
• and
• in response to the sending the request at the second time-slice, the hardware plane storing state information associated with the first process in the memory, and the hardware plane retrieving state information associated with the second process from the memory.