Techniques for integrated circuit clock management using multiple clock generators

An integrated circuit, comprising:

• a phase locked loop (PLL) including a first output configured to provide a first clock signal at a first frequency and a second output configured to provide a second clock signal at the first frequency, wherein the second clock signal is out-of-phase with the first clock signal;
• a first clock generator having a first clock input configured to receive the first clock signal, a second clock input configured to receive the second clock signal, a mode signal input configured to receive a first mode signal, and an output, wherein the output of the first clock generator is configured to provide a first generated clock signal whose effective frequency is based on the first and second clock signals and the first mode signal;
• a second clock generator having a first clock input configured to receive the first clock signal, a second clock input configured to receive the second clock signal, a mode signal input configured to receive a second mode signal, and an output, wherein the output of the second clock generator is configured to provide a second generated clock signal whose actual frequency is based on the first and second clock signals and the second mode signal;
• a static clocked logic circuit having a clock input configured to receive the first generated clock signal;
• and
• a dynamic clocked logic circuit having a clock input configured to receive the second generated clock signal.

A method of providing clock signals, comprising:

• generating first and second clock signals that are substantially in quadrature with each other;
• receiving first and second mode signals corresponding to first and second generated clock signals, respectively;
• providing the first generated clock signal at a first effective frequency based on the first and second clock signals and the first mode signal;
• and
• providing the second generated clock signal at a second effective frequency based on the first and second clock signals and the second mode signal.