Zero-delay serial communications circuitry for serial interconnects

A method for conveying data from a first circuit module on an integrated circuit to a second circuit module on the same integrated circuit over a serial interconnect path on the integrated circuit, comprising:

• receiving serial data from the serial interconnect path using a data sampler in the second circuit module;
• with the data sampler, sampling the received serial data using a multiphase clock to produce multiple sampled data signals;
• with a multiplexer, selecting one of the sampled data signals to serve as a recovered data signal for the second circuit module;
• controlling the multiplexer with a phase pointer signal that indicates which of the sampled data signals is selected;
• determining how much clock phase shift error exists between a current value of the phase pointer signal and an optimum value of the phase pointer signal;
• and
• updating the current value of the phase pointer based on the clock phase shift error, wherein updating the current value of the phase pointer based on the clock phase shift error comprises comparing the clock phase shift error to a threshold error and updating the current value of the phase pointer only when the clock phase shift error is equal to at least the threshold error, wherein the threshold error equals two clock phases of the multiphase clock.

A method for conveying data from a first circuit module on an integrated circuit to a second circuit module on the same integrated circuit over a serial interconnect path on the integrated circuit, comprising:

• receiving serial data from the serial interconnect path using a data sampler in the second circuit module;
• with the data sampler, sampling the received serial data using a multiphase clock to produce multiple sampled data signals;
• with a multiplexer, selecting one of the sampled data signals to serve as a recovered data signal for the second circuit module;
• controlling the multiplexer with a phase pointer signal that indicates which of the sampled data signals is selected;
• determining how much clock phase shift error exists between a current value of the phase pointer signal and an optimum value of the phase pointer signal;
• updating the current value of the phase pointer based on the clock phase shift error;
• and
• maintaining the phase pointer in a shift register, wherein updating the current value of the phase pointer based on the clock phase shift error comprises comparing the clock phase shift error to a threshold error and updating the current value of the phase pointer only when the clock phase shift error equals at least the threshold error, wherein updating the current value of the phase pointer comprises applying shift control signals to the shift register.

A method for conveying data from a first circuit module on an integrated circuit to a second circuit module on the same integrated circuit over a serial interconnect path on the integrated circuit, comprising:

• receiving serial data from the serial interconnect path using a data sampler in the second circuit module;
• with the data sampler, sampling the received serial data using a multiphase clock to produce multiple sampled data signals;
• with a multiplexer, selecting one of the sampled data signals to serve as a recovered data signal for the second circuit module;
• controlling the multiplexer with a phase pointer signal that indicates which of the sampled data signals is selected;
• determining how much clock phase shift error exists between a current value of the phase pointer signal and an optimum value of the phase pointer signal;
• updating the current value of the phase pointer based on the clock phase shift error;
• maintaining the phase pointer in a shift register;
• and
• processing the sampled data signals and the phase pointer with control circuitry, wherein updating the current value of the phase pointer based on the clock phase shift error comprises comparing the clock phase shift error to a threshold error with the control circuitry and updating the current value of the phase pointer only when the clock phase shift error equals at least the threshold error, wherein updating the current value of the phase pointer comprises applying shift control signals to the shift register with the control circuitry.

Circuitry, comprising:

• a data sampler that receives serial data from a serial interconnect path, that receives multiple clock phases that are used to sample the serial data to produce multiple sampled data signals, and an output at which each of the multiple sampled data signals is provided;
• a multiplexer having multiple sample data inputs each of which receives a respective one of the multiple sampled data signals from the data sampler, having a control input to which a phase pointer signal is provided, and having an output at which a selected one of the sampled data signals is provided as a recovered data signal in response to the phase pointer signal;
• and
• control circuitry that receives the sampled data signals from the data sampler and that uses the phase pointer signal and the received sampled data signals to determine how much clock phase shift error exists between a current value of the phase pointer signal and an optimum value of the phase pointer signal, wherein the control circuitry updates the current value of the phase pointer only when the clock phase shift error is equal to at least a threshold error of at least two clock phases.