Pipeline architecture for multi-slot wireless link processing

A wireless device operable to process a multi-slot Time Division Multiple Access (TDMA) signal, wherein the TDMA signal is received over a plurality of time periods as a first section followed by a second section followed by a third section, the wireless device comprising:

• a baseband processor operable to:
• pre-process the third section;
• and
• post-process the first section;
• and
• an equalizer module coupled to the baseband processor and operable to equalize the second section,
• wherein the equalizer module is operable to equalize the second section during the same or substantially the same time period(s) as the baseband processor is operable to pre-process the third section and/or post-process the first section.

A wireless device for processing a multi-slot Time Division Multiple Access (TDMA) signal, wherein the TDMA signal is received over a plurality of time periods as a first section followed by a second section followed by a third section, the wireless device comprising:

• a baseband processor;
• and
• an equalizer module coupled to the baseband processor,
• wherein, in combination, the baseband processor and equalizer module are operable to:
• pre-process the first section;
• pre-process the second section while equalizing the first section;
• post-process the first section while equalizing the second section;
• pre-process the third section while equalizing the second section;
• and
• post-process the second section while equalizing the third section.