Method and system for utilizing a single PLL to clock an array of DDFS for multi-protocol applications

A machine-readable storage having stored thereon, a computer program having at least one code section for processing signals, the at least one code section being executable by a machine for causing the machine to perform steps comprising:

• generating a first signal utilizing a phased-locked-loop (PLL);
• generating a local oscillator signal from said generated first signal in each of a plurality of local oscillator generators directly coupled to said PLL, wherein each of said plurality of local oscillator signals is generated independently of each other by corresponding circuitry that comprises one of a direct digital frequency synthesizer (DDFS) or a digital delay circuit;
• and
• wirelessly communicating utilizing a plurality of protocols in which a transmission carrier frequency is different from a reception carrier frequency, wherein for each of said plurality of protocols said transmission carrier frequency is associated with one of said generated plurality of local oscillator signals and is different from a transmission carrier frequency of another of said plurality of protocols, and said reception carrier frequency is associated with another of said generated plurality of local oscillator signals and is different from a reception carrier frequency of another of said plurality of protocols.

A system for processing signals, the system comprising:

• one or more circuits comprising a phase-locked-loop (PLL) circuit that enables generation of a first signal;
• said one or more circuits comprise a plurality of local oscillator generators directly coupled to said PLL circuit that enable generation of a plurality of local oscillator signals from said generated first signal, wherein each of said plurality of local oscillator signals is generated independently of each other by a corresponding one of said plurality of local oscillator generators that comprises one of a direct digital frequency synthesizer or a digital delay circuit;
• and
• said one or more circuits enable wireless communication utilizing a plurality of protocols in which a transmission carrier frequency is different from a reception carrier frequency, wherein for each of said plurality of protocols said transmission carrier frequency is associated with one of said generated plurality of local oscillator signals and is different from a transmission carrier frequency of another of said plurality of protocols, and said reception carrier frequency is associated with another of said generated plurality of local oscillator signals and is different from a reception carrier frequency of another of said plurality of protocols.