HD physical layer of a wireless communication device

An apparatus comprising:

• a processor;
• a radio frequency (RF) transmitter coupled to and controlled by the processor to transmit data;
• and
• a physical layer circuit coupled to the RF transmitter to encode and decode between a digital signal and a modulated analog signal, the physical layer circuit comprising a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP), wherein the radio frequency (RF) transmitter comprises one crystal to generate immediate frequency (IF) and F, wherein the crystal generates four channels centers between about 57 GHz and about 66 GHz;
• wherein the low rate channels generated by the low rate physical layer circuit (LRP) share a same frequency band as a corresponding high rate channel generated by the high rate physical layer circuit (HRP).

An apparatus comprising:

• a processor;
• a radio frequency (RF) transmitter coupled to and controlled by the processor to transmit data;
• and
• a physical layer circuit coupled to the RF transmitter to encode and decode between a digital signal and a modulated analog signal, the physical layer circuit comprising a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP),
• wherein the low rate channels generated by the low rate physical layer circuit (LRP) share a same frequency band as a corresponding high rate channel generated by the high rate physical layer circuit (HRP), wherein the HRP comprise an outer code circuit, an outer interleaver circuit, and M inner code circuits,
• wherein M is larger than 1 and the outer interleaver comprises a block interleaver that maps consecutive bytes of the outer code codeword to different inner code, and maps the same byte in the outer code codeword to consecutive bits for the inner code.

An apparatus comprising:

• a processor;
• a radio frequency (RF) transmitter coupled to and controlled by the processor to transmit data;
• and
• a physical layer circuit coupled to the RF transmitter to encode and decode between a digital signal and a modulated analog signal, the physical layer circuit comprising a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP),
• wherein the low rate channels generated by the low rate physical layer circuit (LRP) share a same frequency band as a corresponding high rate channel generated by the high rate physical layer circuit (HRP), wherein the LRP is configured to generate a LRP Long Omni data packet and a LRP Short Directional data packet, wherein the LRP Long Omni data packet comprises a LRP preamble, a LRP header, a LRP payload, wherein the LRP preamble comprises a long Omni LRP preamble or a short Omni LRP preamble, wherein the long Omni LRP preamble is configured for beacons and for LRP data packets with blind timing synchronization.

An apparatus comprising:

• a processor;
• a radio frequency (RF) transmitter coupled to and controlled by the processor to transmit data;
• and
• a physical layer circuit coupled to the RF transmitter to encode and decode between a digital signal and a modulated analog signal, the physical layer circuit comprising a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP),
• wherein the low rate channels generated by the low rate physical layer circuit (LRP) share a same frequency band as a corresponding high rate channel generated by the high rate physical layer circuit (HRP), wherein the LRP is configured to generate a LRP Long Omni data packet and a LRP Short Directional data packet, wherein the LRP Long Omni data packet comprises a LRP preamble, a LRP header, a LRP payload, wherein the LRP preamble comprises a long Omni LRP preamble or a short Omni LRP preamble, wherein the long Omni LRP preamble comprises a first automatic gain control (AGC) and signal detection segment, a coarse frequency offset estimation (FOE) and timing recovery segment, a fine FOE and timing recovery segment, and a receiver beam-forming segment, a second AGC segment, and a channel estimation segment.

An apparatus comprising:

• a processor;
• a radio frequency (RF) transmitter coupled to and controlled by the processor to transmit data;
• and
• a physical layer circuit coupled to the RF transmitter to encode and decode between a digital signal and a modulated analog signal, the physical layer circuit comprising a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP),
• wherein the low rate channels generated by the low rate physical layer circuit (LRP) share a same frequency band as a corresponding high rate channel generated by the high rate physical layer circuit (HRP), wherein the LRP is configured to generate a LRP Long Omni data packet and a LRP Short Directional data packet, wherein the LRP Long Omni data packet comprises a LRP preamble, a LRP header, a LRP payload, wherein the LRP preamble comprises a long Omni LRP preamble or a short Omni LRP preamble, wherein the short Omni LRP preamble is about 43 μsec long.

An apparatus comprising:

• a processor;
• a radio frequency (RF) transmitter coupled to and controlled by the processor to transmit data;
• and
• a physical layer circuit coupled to the RF transmitter to encode and decode between a digital signal and a modulated analog signal, the physical layer circuit comprising a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP),
• wherein the low rate channels generated by the low rate physical layer circuit (LRP) share a same frequency band as a corresponding high rate channel generated by the high rate physical layer circuit (HRP), wherein the LRP is configured to generate a LRP Long Omni data packet and a LRP Short Directional data packet, wherein the LRP Long Omni data packet comprises a LRP preamble, a LRP header, a LRP payload, wherein the LRP preamble comprises a long Omni LRP preamble or a short Omni LRP preamble, wherein the short Omni LRP preamble is configured for contention period and for LRP data packets with timing synchronization.

An apparatus comprising:

• a processor;
• a radio frequency (RF) transmitter coupled to and controlled by the processor to transmit data;
• and
• a physical layer circuit coupled to the RF transmitter to encode and decode between a digital signal and a modulated analog signal, the physical layer circuit comprising a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP),
• wherein the low rate channels generated by the low rate physical layer circuit (LRP) share a same frequency band as a corresponding high rate channel generated by the high rate physical layer circuit (HRP), wherein the LRP is configured to generate a LRP Long Omni data packet and a LRP Short Directional data packet, wherein the LRP Long Omni data packet comprises a LRP preamble, a LRP header, a LRP payload, wherein the LRP preamble comprises a long Omni LRP preamble or a short Omni LRP preamble, wherein the short Omni LRP preamble comprises a first automatic gain control (AGC) segment, a second AGC segment, a signal detection and time synch segment, a receiver beam-forming segment, a third AGC segment, and a channel estimation segment.

An apparatus comprising:

• a processor;
• a radio frequency (RF) transmitter coupled to and controlled by the processor to transmit data;
• and
• a physical layer circuit coupled to the RF transmitter to encode and decode between a digital signal and a modulated analog signal, the physical layer circuit comprising a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP),
• wherein the low rate channels generated by the low rate physical layer circuit (LRP) share a same frequency band as a corresponding high rate channel generated by the high rate physical layer circuit (HRP), wherein the LRP is configured to generate a LRP Long Omni data packet, an LRP Beam-formed data packet, and a LRP Short Directional data packet, wherein the LRP Beam-formed data packet comprises a LRP Beam-formed preamble, a LRP Beam-formed header, and a LRP Beam-formed payload.

An apparatus comprising:

• a processor;
• a radio frequency (RF) transmitter coupled to and controlled by the processor to transmit data;
• and
• a physical layer circuit coupled to the RF transmitter to encode and decode between a digital signal and a modulated analog signal, the physical layer circuit comprising a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP),
• wherein the low rate channels generated by the low rate physical layer circuit (LRP) share a same frequency band as a corresponding high rate channel generated by the high rate physical layer circuit (HRP), wherein the LRP is configured to generate a LRP Long Omni data packet and a LRP Short Directional data packet, wherein the LRP short directional data packet comprises a LRP short directional preamble, and a LRP short directional header.

An apparatus comprising:

• a processor;
• a radio frequency (RF) transmitter having a digitally controlled phased array antenna coupled to and controlled by the processor to transmit data or content;
• an interface to a wireless communication channel coupled to the processor to communicate antenna information relating to the use of the phased array antenna and to communicate information to facilitate receiving the data or playing the content at another location;
• and
• a physical layer circuit coupled to the RF transmitter and the interface for encoding and decoding between a digital signal and a modulated analog signal, the physical layer circuit comprising a high rate physical layer circuit (HRP) and a low rate physical layer circuit (LRP),
• wherein the low rate channels generated by the low rate physical layer circuit (LRP) share a same frequency band as a corresponding high rate channel generated by the high rate physical layer circuit (HRP);
• and
• wherein the HRP comprises an outer code circuit, an outer interleaver circuit, M inner code circuits, where M is larger than 1 and the outer interleaver comprises a block interleaver that maps consecutive bytes of an outer code codeword to a different inner code, and maps the same byte in the outer code codeword to consecutive bits for the inner code.

An apparatus comprising:

• a processor;
• a radio frequency (RF) transmitter coupled to and controlled by the processor to transmit content;
• a physical layer circuit coupled to the RF transmitter and the processor for encoding and decoding between a digital signal and a modulated analog signal,
• wherein the physical layer circuit comprises a low rate physical layer circuit (LRP) capable of operating in a directional mode or an omni-directional mode for the RF transmitter,
• wherein in the omni-directional mode, the physical layer circuit is to generate a same signal replicated N times, each replication using a different TX antenna phase pattern, and wherein in the directional mode, the physical layer circuit is to generate a same signal replicated N+1 times, each replication uses a same optimal TX antenna phase pattern, the optimal TX antenna phase pattern feedback to a back channel transmitter from a back channel receiver.