Providing a fully non-blocking switch in a supernode of a multi-tiered full-graph interconnect architecture

A computer program product, for transmitting data from a first processor to a second processor in a first set of processors of a data processing system, each processor in the data processing system having a switch, comprising a non-transitory computer readable medium having a computer readable program, wherein the computer readable program, when executed in a computing device, causes the computing device to:

• create a set of virtual channels in each switch;
• transmit the data from the first processor to the second processor through a path comprising a second set of processors in the data processing system;
• and
• store, in each processor of the second set of processors, the data in a virtual channel of a corresponding switch before transmitting the data to a next processor in a subset of processors, wherein the virtual channel of the corresponding switch in which the data is stored corresponds to a position of the processor in the path through which the data is transmitted from the first processor to the second processor, wherein a number of virtual channels created in each switch is determined based on a length of a longest indirect path in the data processing system and wherein the number of virtual channels created in each switch is equal to a number of ports of a corresponding processor multiplied by a number of processors in the longest indirect path in the data network.

A data processing system, comprising:

• a first set of processors, each processor having a switch, the first set of processors further comprising a first processor and a second processor;
• and
• a set of switches, each processor having an associated switch in the set of switches, wherein logic in the switches operate to:
• create a set of virtual channels in the switches;
• transmit data from the first processor to the second processor through a path comprising a second set of processors in the data processing system;
• and
• store, in each processor of the second set of processors, the data in a virtual channel of a corresponding switch before transmitting the data to a next processor in a subset of processors, wherein the virtual channel of the corresponding switch in which the data is stored corresponds to a position of the processor in the path through which the data is transmitted from the first processor to the second processor, wherein a number of virtual channels created in each switch is determined based on a length of a longest indirect path in the data processing system and wherein the number of virtual channels created in each switch is equal to a number of ports of a corresponding processor multiplied by a number of processors in the longest indirect path in the data network.