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US 8,014,226 B2Granted
Integrated circuit memory with word line driving helper circuits
AssigneeArm Limited
InventorsGus Yeung, Amarnath Shanmugam, Yew Keong Chong, Jacek Wiatrowski
Life of this patent
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Abstract
An integrated circuit memory 2 incorporates a first array of bit cells 4 and a second array of bit cells 6 with word line driver circuitry 8 disposed therebetween. Word line helper circuitry 18, 20 is disposed at the opposite edges of the array 4, 6 to the word line driver circuitry 8. The helper circuitry is responsive to the word line signal on a word line 12 being driven towards an asserted value to switch on and further drive the word line signal towards the asserted value. The helper circuitry is switched off by a global reset signal, which may be a self-timed global reset signal.
Claims18
An integrated circuit memory comprising:
- a first array of memory cells;
- a second array of memory cells;
- word line driver circuitry located between said first array and said second array;
- a first plurality of word lines extending from a first side of said word line driver circuitry through said first array;
- a second plurality of word lines extending from a second side of said word line driver circuitry through said second array;
- a first plurality of word line helper circuits coupled to respective word lines of said first plurality of word lines;
- and
- a second plurality of word line helper circuits coupled to respective word lines of said second plurality of word lines;
- wherein
- said word line driver circuitry is responsive to an access request to drive a first word line signal upon a first driven word line of said first plurality of word lines toward a first asserted value and to drive a second word line signal upon a second driven word line of said second plurality of word lines toward a second asserted value;
- said first plurality of word line helper circuits include a first word line helper circuit coupled to said first driven word line and switched by said first word line signal being driven toward said first asserted value to further drive said first word line signal toward said first asserted value such that said first word line signal value more rapidly reaches said first asserted value;
- and
- said second plurality of word line helper circuits include a second word line helper circuit coupled to said second driven word line and switched by said second word line signal being driven toward said second asserted value to further drive said second word line signal toward said second asserted value such that said second word line signal value more rapidly reaches said second asserted value.
10 more elements
An integrated circuit memory as claimed 1, wherein said first word line helper circuit is responsive to a reset signal to cease driving said first word line toward said first asserted value and said second word line helper circuit is responsive to said reset signal to cease driving said second word line toward said second asserted value.
An integrated circuit memory comprising:
- a first array of memory cell means;
- a second array of memory cell means;
- word line driver means located between said first array and said second array;
- a first plurality of word lines extending from a first side of said word line driver means through said first array;
- a second plurality of word lines extending from a second side of said word line driver means through said second array;
- a first plurality of word line helper means coupled to respective word lines of said first plurality of word lines;
- and
- a second plurality of word line helper means coupled to respective word lines of said second plurality of word lines;
- wherein
- said word line driver means is responsive to an access request to drive a first word line signal upon a first driven word line of said first plurality of word lines toward a first asserted value and to drive a second word line signal upon a second driven word line of said second plurality of word lines toward a second asserted value;
- said first plurality of word line helper means include a first word line helper means coupled to said first driven word line and switched by said first word line signal being driven toward said first asserted value to further drive said first word line signal toward said first asserted value such that said first word line signal value more rapidly reaches said first asserted value;
- and
- said second plurality of word line helper means include a second word line helper means coupled to said second driven word line and switched by said second word line signal being driven toward said second asserted value to further drive said second word line signal toward said second asserted value such that said second word line signal value more rapidly reaches said second asserted value.
10 more elements
A method of operating an integrated circuit memory having:
- a first array of memory cells;
- a second array of memory cells;
- word line driver circuitry located between said first array and said second array;
- a first plurality of word lines extending from a first side of said word line driver means through said first array;
- a second plurality of word lines extending from a second side of said word line driver means through said second array;
- a first plurality of word line helper circuits coupled to respective word lines of said first plurality of word lines;
- and
- a second plurality of word line helper circuits coupled to respective word lines of said second plurality of word lines;
- said method comprising the steps of:
- in response to an access request, driving a first word line signal upon a first driven word line of said first plurality of word lines toward a first asserted value and driving a second word line signal upon a second driven word line of said second plurality of word lines toward a second asserted value;
- using a first word line helper circuit of said first plurality of word line helper circuits and switched by said first word line signal being driven toward said first asserted value to further drive said first word line signal toward said first asserted value such that said first word line signal value more rapidly reaches said first asserted value;
- and
- using a second word line helper circuit of said second plurality of word line helper circuits and switched by said second word line signal being driven toward said second asserted value to further drive said second word line signal toward said second asserted value such that second first word line signal value more rapidly reaches said second asserted value.
10 more elements
Dependencies are inferred from the claim text.