Semiconductor device

A semiconductor device supplied a first external voltage and a second external voltage, supplied externally, comprising;

• a power supply module supplied with said first external voltage;
• a logic circuit portion for performing a logical operation based on data to be input, said logic circuit portion supplied with said second external voltage;
• and
• a memory macro, wherein
• said memory macro includes:
• a memory array having a plurality of memory cells, each holding data to be used in said logic circuit portion, arranged in a matrix;
• a first load circuit having a sense amplifier for sensing data on a bit line connected to a memory cell;
• and
• a second load circuit having a data input/output circuit for performing data input/output between said logic circuit portion and a memory cell, said second load circuit being supplied with said second external voltage, wherein
• said power supply module for stepping down said first external voltage to supply said memory array and said first load circuit with a internal voltage lower than said first internal voltage.

A semiconductor device comprising:

• a first power supply pad, externally supplying a first external voltage;
• a second power supply pad, externally supplying a second external voltage lower than said first external voltage;
• a third power supply pad, externally supplying a ground voltage lower than said second external voltage;
• a power supply module for bucking said first external voltage to supply an internal buck voltage;
• a logic circuit portion for performing a logical operation based on data to be input;
• and
• a memory macro, wherein
• said memory macro includes:
• a memory array having a plurality of memory cells, each holding data to be used in said logic circuit portion, arranged in a matrix;
• a first load circuit having a sense amplifier for sensing data on a bit line connected to a memory cell, said first load circuit being supplied with said internal buck voltage;
• and
• a second load circuit having a data input/output circuit for performing data input/output between said logic circuit portion and a memory cell, said second load circuit being supplied with said second external voltage, wherein
• said second load circuit further includes a row decoder for selecting one of rows in said memory array,
• a column decoder for selecting one of columns in said memory array, a data path connected between said sense amplifier and said data input/output circuit, and
• a control circuit for receiving a first signal and outputting control signals to said row decoder, said column decoder and said data path, respectively.