Control of inputs to a memory device
AssigneeMicron Technology, Inc.
InventorsYutaka Ito, Masayoshi Nomura, Keiichiro Abe
Life of this patent
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Abstract
A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy mode in the memory device, a self-refresh signal causes the control signal to disable the external inputs. With the external inputs disabled, command hazards are reduced when exiting drowsy mode.
Claims23
A method of controlling signals in a semiconductor integrated circuit device, the method comprising:
- enabling a generator state signal, the generator state signal operative to indicate states of a voltage generator;
- disabling a self-refresh signal, the self-refresh signal operative to enable refresh cycles in a semiconductor memory device;
- controlling a signal based at least in part on the self-refresh signal and on the generator state signal in communication with the signal;
- and
- controlling an input based at least in part on the signal, the input in communication with the signal and with a command decoder.
A method of controlling signals in a semiconductor integrated circuit device, the method comprising:
- controlling a signal based at least in part on a self-refresh signal in communication with the signal, the self-refresh signal operative to enable refresh cycles in a semiconductor memory device;
- controlling an input based at least in part on the signal, the input in communication with the signal and with a command decoder;
- supplying power to a path-gate with a secondary voltage generator in the event that a main voltage generator powers off, the secondary voltage generator in communication with the path-gate, the path-gate in communication with the input, wherein the path-gate is operative to transmit the input to the command decoder;
- and
- enabling with a clamp transistor the main voltage generator to assist the secondary voltage generator, the clamp transistor in communication with the secondary voltage generator and with the main voltage generator.
A semiconductor integrated circuit device comprising:
- a voltage generator, wherein a generator state signal operates to indicate states of the voltage generator;
- a self-refresh signal operative to enable refresh cycles in a semiconductor memory device;
- an input in communication with a command decoder;
- and
- interface logic in communication with the input and the command decoder, wherein the interface logic controls the input based at least in part on the self-refresh signal and the generator state signal.
A semiconductor integrated circuit device comprising:
- means for controlling a signal based at least in part on a self-refresh signal in communication with the signal, the self-refresh signal operative to enable refresh cycles in a semiconductor memory device;
- means for controlling an input based at least in part on the signal, the input in communication with the signal and with a command decoder;
- means for supplying power to a path-gate with a secondary voltage generator in the event that a main voltage generator powers off, the secondary voltage generator in communication with the path-gate, the path-gate in communication with the input, wherein the path-gate is operative to transmit the input to the command decoder;
- and
- means for enabling with a clamp transistor a main voltage generator to assist a secondary voltage generator, the clamp transistor in communication with the secondary voltage generator and with the main voltage generator.
Dependencies are inferred from the claim text.