Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorYoshihiro Ueda
Life of this patent
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Abstract
A semiconductor memory device includes a memory cell having a resistance which differs based on stored data, a bit line connected to the memory cell, a first MOSFET which clamps the bit line to a read voltage when reading data, a sense amplifier which detects the stored data in the memory cell based on a current flowing through the bit line, a first switch element which connects the sense amplifier to a drain of the first MOSFET, a second switch element which connects a source of the first MOSFET to the bit line, a third switch element which connects the drain of the first MOSFET to a ground terminal, and a fourth switch element which connects the source of the first MOSFET to a ground terminal.
Claims20
A semiconductor memory device comprising:
- a memory cell configured to store data, comprising a resistance configured to vary based on the stored data;
- a bit line connected to the memory cell;
- a first Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) configured to hold the bit line to a read voltage while reading data;
- a sense amplifier configured to detect the stored data in the memory cell based on a current flowing through the bit line;
- a first switch configured to connect the sense amplifier to a drain of the first MOSFET;
- a second switch configured to connect a source of the first MOSFET to the bit line;
- a third switch configured to connect the drain of the first MOSFET to a ground terminal;
- and
- a fourth switch configured to connect the source of the first MOSFET to a ground terminal,
- wherein the first and second switches are on and the third and fourth switches are off when the sense amplifier is active, and
- the first and second switches are off and the third and fourth switches are on when the sense amplifier is inactive.
A semiconductor memory device comprising:
- a memory cell configured to store data, comprising a resistance configured to vary based on the stored data;
- a bit line connected to the memory cell;
- a first MOSFET configured to hold the bit line to a read voltage while reading data;
- a sense amplifier configured to detect the stored data in the memory cell based on a current flowing through the bit line;
- a second MOSFET configured to connect the sense amplifier to a drain of the first MOSFET;
- a third MOSFET configured to connect a source of the first MOSFET to the bit line;
- a fourth MOSFET configured to connect the drain of the first MOSFET to a ground terminal;
- and
- a fifth MOSFET configured to connect the source of the first MOSFET to a ground terminal,
- wherein the second and third MOSFETs are on and the fourth and fifth MOSFETs are off when the sense amplifier is active, and
- the second and third MOSFETs are off and the fourth and fifth MOSFETs are on when the sense amplifier is inactive.
Dependencies are inferred from the claim text.