Cache array power savings through a design structure for valid bit detection

A cache access memory comprising:

• an address decoder in the cache access memory for sending a memory access to a non-gated wordline driver and a gated wordline driver associated with the memory access;
• the non-gated wordline driver for determining whether the memory access is a write access or a read access and for outputting the data stored in a valid bit memory cell to the gated wordline driver in response to the non-gated wordline driver determining the memory access as being the read access;
• and
• the gated wordline driver for determining whether the memory access is the write access or the read access, for determining whether the data from the valid bit memory cell from the non-gated wordline driver indicates either valid data or invalid data in response to the gated wordline driver determining the memory access as being the read access, and for denying an output of the data in a row of memory cells associated with the gated wordline driver in response to the data being invalid.

A design structure embodied in a machine readable medium used in a design process, the design structure comprising:

• a first design structure element representing a non-gated wordline driver that:
• receives a memory access from a second design structure element representing an address decoder;
• determines whether the memory access is a write access or a read access;
• and
• responsive to determining the memory access as being the read access, outputs the data stored in a third design structure element representing a valid bit memory cell to a fourth design structure element representing a gated wordline driver;
• and
• the fourth design structure element representing the gated wordline driver:
• determines whether the memory access is the write access or the read access;
• responsive to the memory access as being the read access, determines whether the data from the valid bit memory cell from the non-gated wordline driver indicates either valid data or invalid data;
• and
• responsive to the data being invalid, denies an output of the data in a fifth design structure element representing a row of memory cells associated with the fourth design structure element representing the gated wordline driver.