Semiconductor memory device
AssigneeElpida Memory, Inc.
InventorJunji Yamada
Life of this patent
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Abstract
A semiconductor memory device is constituted of a plurality of fuses (or anti-fuses) used for internal voltage adjustment or timing adjustment after manufacturing, a selector for sequentially selecting the fuses, and a single-direction latch circuit for latching a fuse breakdown determination result which is produced by determining whether or not each fuse selected by the selector is broken down and which is varied in a single direction from the low level to the high level or in a single direction from the high level to the low level. The semiconductor memory device allows the fuse breakdown determination to progress with a high reliability by use of a relatively small chip area and to cope with a failure in which one or more fuses are accidentally short-circuited to an unwanted potential.
Claims17
A semiconductor device comprising:
- a plurality of nonvolatile elements;
- and
- a flip-flop having a set terminal and a reset terminal, which collectively stores a plurality of determination results with respect to the plurality of nonvolatile elements,
- wherein an output terminal of the flip-flop is changed from a first logic level, which is initially set to the flip-flop via the reset terminal, to a second logic level in response to the plurality of determination results sequentially input into the set terminal of the flip-flop.
A semiconductor device comprising:
- a plurality of fuses or anti-fuses;
- a selector for sequentially selecting the plurality of fuses or anti-fuses;
- and
- a single-direction latch circuit for latching a fuse breakdown determination result representing a breakdown of the fuse or anti-fuse selected by the selector only when the fuse breakdown determination result is varied in a single direction from a low level to a high level or in a single direction from the high level to the low level.
A semiconductor device comprising:
- a plurality of fuses or anti-fuses;
- and
- a single-direction latch circuit for sequentially inputting a plurality of fuse breakdown determination results regarding the plurality of fuses or anti-fuses, thus outputting a logical sum or a logical product based on the plurality of fuse breakdown determination results.
Dependencies are inferred from the claim text.