Semiconductor device and control method thereof
AssigneeRenesas Electronics Corporation
InventorShunya Nagata
Life of this patent
Estimating the term…
Abstract
Disclosed is a memory circuit that includes a plurality of columns of bit line pairs, each bit line pair including True and Bar bit lines, between which at least a memory cell is connected; a sense amplifier that has True and Bar terminals and that performs differential amplification; and a switching circuit that selects one of: a straight connection in which the True and Bar bit lines of a selected column bit line pair are connected to the True and Bar terminals of the sense amplifier, respectively; and a cross connection in which the True and Bar bit lines of a selected column bit line pair are connected to the Bar and True terminals of the sense amplifier, respectively.
Claims9
A semiconductor device comprising:
- a plurality of columns of bit line pairs, each bit line pair including True and Bar bit lines, between which at least a memory cell is connected;
- a sense amplifier that includes True and Bar terminals and that performs differential amplification;
- a switching circuit that selects one out of:
- a straight connection in which the True and Bar bit lines of a selected column bit line pair are connected to the True and Bar terminals of the sense amplifier, respectively, and
- a cross connection in which the True and Bar bit lines of a selected column bit line pair are connected to the Bar and True terminals of the sense amplifier, respectively;
- and
- an IO (input/output) line pair for the plurality of columns of bit line pairs, the IO line pair including True and Bar IO lines, the True and Bar terminals of the sense amplifier being connected to True and Bar IO lines, respectively, wherein:
- a bit line pair of a selected column among the plurality of columns of bit line pairs is connected to the IO line pair via a column selection circuit that is in an on state, and
- the switching circuit is arranged on the IO line pair between connection portions of the IO line pair and column selection circuits provided for the plurality of columns and connection nodes of the IO line pair and the True and Bar terminals of the sense amplifier.
A control method of a semiconductor device comprising a memory circuit including a plurality of columns of bit line pairs, each bit line pair including True and Bar bit lines, between which at least a memory cell is connected, and a sense amplifier that includes True and Bar terminals and that performs differential amplification, the method comprising:
- storing information on a combination of the sense amplifier and the bit line, in a storage element, the combination having a predetermined operation limit detected by a test;
- based on the information stored in the storage element, selecting one out of:
- a straight connection in which True and Bar bit lines of a selected column bit line pair are connected to the True terminal and the Bar terminal of the sense amplifier, respectively, and
- a cross connection in which True and Bar bit lines of a selected column bit line pair are connected to the Bar terminal and the True terminal of the sense amplifier;
- detecting, by a test before product shipping, a combination of a memory cell and the sense amplifier, with a predetermined operation limit, and storing detected information in a non-volatile storage element;
- transmitting, when a product is being operated after shipping, information stored in the non-volatile storage element to a memory circuit;
- and
- based on the information stored in the non-volatile storage element, either connecting True and Bar bit lines of a selected column bit line pair to a True terminal and a Bar terminal of the sense amplifier, or connecting True and Bar bit lines of the selected column bit line pair to the Bar terminal and the True terminal of the sense amplifier.
Dependencies are inferred from the claim text.