Semiconductor device
AssigneeFujitsu Semiconductor Limited
InventorSatoshi Torii
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a first memory cell which includes a first memory transistor and a first selector transistor. The semiconductor device further includes a second memory cell which includes a second memory transistor and a second selector transistor. The semiconductor device further includes a first word line electrically coupled to a gate electrode of the first memory transistor and to a gate electrode of the second selector transistor, and a second word line electrically coupled to a gate electrode of the second memory transistor and to a gate electrode of the first selector transistor. The semiconductor device further includes a first source line electrically coupled to a source region of the first memory transistor and to a source region of the second memory transistor.
Claims20
A semiconductor device comprising:
- a first memory cell which includes a first memory transistor and a first selector transistor;
- a second memory cell which includes a second memory transistor and a second selector transistor;
- a first word line electrically coupled to a gate electrode of the first memory transistor and to a gate electrode of the second selector transistor;
- a second word line electrically coupled to a gate electrode of the second memory transistor and to a gate electrode of the first selector transistor;
- and
- a first source line electrically coupled to a source region of the first memory transistor and to a source region of the second memory transistor.
A semiconductor device comprising:
- a first memory cell which includes a first memory transistor and a first selector transistor;
- a second memory cell which includes a second memory transistor and a second selector transistor;
- a third memory cell which includes a third memory transistor, and includes a third selector transistor which shares a first drain region with the first selector transistor;
- a fourth memory cell which includes a fourth memory transistor, and which includes a fourth selector transistor which shares a second drain region with the second selector transistor;
- a first word line electrically coupled to a gate electrode of the first memory transistor and to a gate electrode of the second memory transistor;
- a second word line electrically coupled to a gate electrode of the third memory transistor and to a gate electrode of the fourth memory transistor;
- a first source line electrically coupled to a source region of the first memory transistor and to a source region of the fourth memory transistor;
- a second source line electrically coupled to a source region of the second memory transistor;
- a third source line electrically coupled to a source region of the third memory transistor;
- a first bit line electrically coupled to the first shared drain region;
- and
- a second bit line electrically coupled to the second shared drain region.
Dependencies are inferred from the claim text.