Back to results
US 8,014,199 B2Granted
Memory system with switch element
AssigneeSpansion LLC
InventorMasao Taguchi
Life of this patent
Estimating the term…
Abstract
A memory system is provided forming a switch element having a first side and a second side, forming a cell transistor having a gate terminal, forming a memory cell, having the switch element and the cell transistor, with the gate terminal connected to the second side, connecting a word line and the memory cell at the first side, connecting a bit line and the memory cell, and connecting a reference source and the memory cell.
Claims26
A method for manufacturing a memory system comprising:
- forming a switch element with resistive change having a first side and a second side;
- forming a cell transistor having a gate terminal, the cell transistor is a junction field effect transistor;
- forming a memory cell, having the switch element and the cell transistor, with the gate terminal connected to the second side, the memory cell is a resistive change memory cell;
- connecting a word line and the memory cell at the first side, including connecting a voltage source to the word line, the voltage source provides a negative voltage value;
- connecting a bit line and the memory cell, the bit line provides a current path;
- and
- connecting a reference source only to a source of the memory cell, the reference source is a reference voltage.
4 more elements
A memory system comprising:
- a switch element with resistive change having a first side and a second side;
- a cell transistor having a gate terminal is a junction field effect transistor;
- a memory cell, having the switch element and the cell transistor, with the gate terminal connected to the second side is a resistive change memory cell;
- a voltage source connected to a word line connected with the memory cell at the first side, the voltage source provides a negative voltage value;
- a bit line connected with the memory cell provides a current path;
- and
- a reference source connected with only a source of the memory cell is a reference voltage.
4 more elements
A method for manufacturing a memory system comprising:
- forming a metal-insulator-metal element having a first side and a second side;
- forming a junction field effect transistor having a gate terminal, a source terminal, and a drain terminal;
- forming a memory cell, having the metal-insulator-metal element and the junction field effect transistor, with the gate terminal connected to the second side;
- connecting a word line and the memory cell at the first side, including connecting a voltage source to the word line, the voltage source provides a negative voltage value;
- connecting a bit line and the memory cell with the junction field effect transistor, wherein the junction field effect transistor has a first block select connected to the gate terminal, the source terminal connected to the memory cell, and the drain terminal connected to the bit line;
- connecting a ground only to the source terminal of the junction field effect transistor of the memory cell wherein the junction field effect transistor has a second block select connected to the gate terminal, the source terminal connected to the ground, and the drain terminal connected to the memory cell;
- and
- connecting a sense circuit and the bit line.
5 more elements
A memory system comprising:
- a metal-insulator-metal element having a first side and a second side;
- a junction field effect transistor having a gate terminal, a source terminal, and a drain terminal;
- a memory cell, having the metal-insulator-metal element and the junction field effect transistor, with the gate terminal connected to the second side;
- a word line connected to the memory cell at the first side, a voltage source connected to the word line, the voltage source provides a negative voltage value;
- a bit line connected to the memory cell with the junction field effect transistor, wherein the junction field effect transistor has a first block select connected to the gate terminal, the source terminal connected to the memory cell, and the drain terminal connected to the bit line;
- a ground only to the source terminal of the junction field effect transistor of the memory cell wherein the junction field effect transistor has a second block select connected to the gate terminal, the source terminal connected to the ground, and the drain terminal connected to the memory cell;
- and
- a sense circuit connected to the bit line.
5 more elements
Dependencies are inferred from the claim text.