US 8,014,198 B2Granted

Nonvolatile semiconductor memory device

AssigneeFujitsu Semiconductor Limited

InventorsSatoshi Torii, Kazuhiro Mizutani, Toshio Nomura, Masayoshi Asano, Ikuto Fukuoka, Hiroshi Mawatari, Motoi Takahashi

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Abstract

A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.

Claims16

Dependent claims

A nonvolatile semiconductor memory device comprising:

a memory cell array of a plurality of memory cells arranged in a matrix, which each include a selecting transistor, and a memory cell transistor connected to the selecting transistor;
a plurality of bit lines each commonly connecting drains of a plurality of the selecting transistors present in one and the same column;
a plurality of first word lines each commonly connecting gate electrodes of a plurality of the memory cell transistors present in one and the same row;
a plurality of second word lines each commonly connecting select gates of a plurality of the selecting transistors present in one and the same row;
a plurality of source lines each commonly connecting sources of a plurality of the memory cell transistors present in one and the same row;
a column decoder connected to said plurality of bit lines and controlling a potential of said plurality of bit lines;
a voltage application circuit connected to said plurality of first word lines and controlling a potential of said plurality of first word lines;
a first row decoder connected to said plurality of second word lines and controlling a potential of said plurality of second word lines;
and
a second row decoder connected to said plurality of source lines and controlling a potential of said plurality of source lines,
the column decoder being formed of a circuit whose withstand voltage is lower than a withstand voltage of the voltage application circuit and a withstand voltage of the second row decoder, and
the first row decoder being formed of a circuit whose withstand voltage is lower than the withstand voltage of the voltage application circuit and the withstand voltage of the second row decoder,
wherein information is written into a selected one of the memory cells by applying a first voltage which gradually rises selectively to one of the first word lines by the voltage application circuit;
and applying a second voltage to one of the source lines by the second row decoder.

11 more elements

A nonvolatile semiconductor memory device comprising:

a memory cell array of a plurality of memory cells arranged in a matrix, which each include a selecting transistor, and a memory cell transistor connected to the selecting transistor;
a plurality of bit lines each commonly connecting drains of a plurality of the selecting transistors present in one and the same column;
a plurality of first word lines each commonly connecting gate electrodes of a plurality of the memory cell transistors present in one and the same row;
a plurality of second word lines each commonly connecting select gates of a plurality of the selecting transistors present in one and the same row;
a plurality of source lines each commonly connecting sources of a plurality of the memory cell transistors present in one and the same row;
a column decoder connected to said plurality of bit lines and controlling a potential of said plurality of bit lines;
a voltage application circuit connected to said plurality of first word lines and controlling a potential of said plurality of first word lines;
a first row decoder connected to said plurality of second word lines and controlling a potential of said plurality of second word lines;
and
a second row decoder connected to said plurality of source lines and controlling a potential of said plurality of source lines,
the column decoder being formed of a circuit whose withstand voltage is lower than a withstand voltage of the voltage application circuit and a withstand voltage of the second row decoder, and
the first row decoder being formed of a circuit whose withstand voltage is lower than the withstand voltage of the voltage application circuit and the withstand voltage of the second row decoder, wherein
said plurality of bit lines are respectively connected to the column decoder via first protection transistors, and
said plurality of second word lines are respectively connected the first row decoder via second protection transistors, and
said nonvolatile semiconductor memory device further comprising
a first control circuit controlling said plurality of first protection transistors and said plurality of second protection transistors.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/411,938Filed 26 Mar 2009 · continuation
Priority: 29 Sep 2006
Published: US 2009/0180320 A116 Jul 2009
Granted: 6 Sep 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11C 16/0433
Comprising cells containing floating gate transistors: comprising cells containing a single floating gate transistor and one or more separate…
G11C 16/10
Auxiliary circuits, e.g. for writing into memory: programming or data input circuits
H10B 41/40
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the peripheral circuit region
H10B 41/41
Characterised by the peripheral circuit region: of a memory region comprising a cell select transistor, e.g. NAND