Semiconductor memory
AssigneePanasonic Corporation
InventorsToshikazu Suzuki, Yoshinobu Yamagami, Satoshi Ishikura
Life of this patent
Estimating the term…
Abstract
In a semiconductor memory including word lines and bit lines arranged in a matrix and a plurality of memory cells provided at intersections of the word lines and the bit lines, a bit line precharge circuit is provided for controlling the potential of a low-data holding power supply coupled to memory cells provided on a corresponding one of the bit lines. In a write operation, the bit line precharge circuit controls the potential of a low-data holding power supply of a memory cell corresponding to a selected bit line to be higher than the potential of a low-data holding power supply of a memory cell corresponding to an unselected bit line.
Claims20
A semiconductor memory, comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells, each connected to at least one of the plurality of word lines and at least one of the plurality of bit lines, and including two cross-coupled inverter circuits for holding a pair of high data and low data;
- and
- a low-data holding power supply control circuit for controlling a potential of a low-data holding power supply coupled to the plurality of memory cells,
- wherein the low-data holding power supply control circuit controls, in a write operation, a potential of a low-data holding power supply of at least one of the plurality of memory cells which is selected for the write operation to be higher than a potential of a low-data holding power supply of at least one of the plurality of memory cells when not in a writing operation.
A semiconductor memory, comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells, each connected to at least one of the plurality of word lines and at least one of the plurality of bit lines and including two cross-coupled inverter circuits for holding a pair of high data and low data;
- and
- a low-data holding power supply control circuit for controlling a potential of a low-data holding power supply coupled to the plurality of memory cells,
- wherein the low-data holding power supply control circuit includes a first transistor connected to a first power supply and a second transistor connected to a second power supply, and supplies a potential between the first and second power supplies to the low-data holding power supply line in a write operation.
A semiconductor memory, comprising:
- a memory cell connected to at least one word line and at least one bit line, and including two cross-coupled inverter circuits for holding a pair of high data and low data;
- and
- a low-data holding power supply control circuit for controlling a potential of a low-data holding power supply coupled to the memory cell,
- wherein the low-data holding power supply control circuit controls a potential of the low-data holding power supply of the memory cell in a write operation to be higher than a potential of the low-data holding power supply of the memory cell when not in a writing operation.
Dependencies are inferred from the claim text.