Radiation hardened memory cell
AssigneeXilinx, Inc.
InventorAustin H. Lesea
Life of this patent
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Abstract
A memory cell has a data value storage circuit and a data address circuit that includes a first address transistor formed in a first address transistor well and a second address transistor formed in a second address transistor well. The first address transistor is coupled between a data node and the second address transistor, and the second address transistor is coupled between the first address transistor and the data value storage circuit. The first address transistor well is coupled to an intermediate node between the first address transistor and the second address transistor, and the second address transistor well is coupled to a ground terminal.
Claims18
A memory cell, comprising:
- a data node;
- a data value storage circuit;
- a data address circuit including a first address transistor formed in a first address transistor well and a second address transistor formed in a second address transistor well, wherein:
- the first address transistor is coupled between the data node and the second address transistor,
- the second address transistor is coupled between the first address transistor and the data value storage circuit,
- each of the first address transistor and the second address transistor are controlled by an address control line,
- the first address transistor well is coupled to an intermediate node between the first address transistor and the second address transistor, and
- the second address transistor well is coupled to a ground terminal.
A method of operating a memory cell, comprising:
- providing a memory cell having an address circuit, the address circuit including a first address transistor in a first address transistor well and a second address transistor in a second address transistor well, the first and second address transistors being coupled in series between a data node and a data value storage circuit;
- wherein the first address transistor well is coupled to an intermediate node between the first address transistor and the second transistor, and the second address transistor well is coupled to a ground terminal;
- turning on the first address transistor and the second address transistors;
- writing a data value to the data value storage circuit;
- turning off the first address transistor and second address transistors;
- and
- exposing the memory cell to ionizing radiation so as to create charge in one of the first address transistor well or the second transistor well, the charge being isolated to one of the first address transistor well or the second address transistor well so as to not disturb the data value.
Dependencies are inferred from the claim text.