Array substrate for in-plane switching mode liquid crystal display device and method of fabricating the same

A method of fabricating an array substrate for an in-plane switching mode liquid crystal display device, comprising:

• forming a gate line, a gate electrode, a first common line, and first common electrodes on a substrate, the gate electrode connected to the gate line, the first common electrodes connected to the first common line;
• forming a gate insulating layer on the gate line, the gate electrode, the first common line, and the first common electrodes;
• forming a semiconductor layer on the gate insulating layer, source and drain electrodes on the semiconductor layer and spaced apart from each other, and a data line connected to the source electrode and crossing the gate line;
• forming a passivation layer on the source electrode, the drain electrode and the data line, the passivaton layer having a data contact hole exposing the data line, a drain contact hole exposing the drain electrode and at least one common contact hole exposing the first common electrodes;
• and
• forming a plurality of pixel electrodes, a second common line, a second common electrode and an auxiliary data line on the passivation layer,
• wherein the plurality of pixel electrodes and the second common electrode are disposed between the first common electrodes and alternately arranged with each other,
• the plurality of pixel electrodes are connected to the drain electrode through the drain contact hole,
• the second common line is connected to the first common electrodes through the at least one common contact hole, and
• the auxiliary data line is connected to the data line through the data contact hole.

A liquid crystal display device, comprising:

• a first substrate including:
• a gate line and a data line crossing the gate line on a base substrate, so as to define a pixel region,
• an auxiliary data line disposed over the data line and connected to the data line;
• a thin film transistor connected to the gate line and the data line,
• a plurality of pixel electrodes disposed in the pixel region and connected to the thin film transistor,
• a first common line extending substantially parallel to the gate line, and
• a plurality of common electrodes alternately arranged with the plurality of pixel electrodes in the pixel region and including first common electrodes disposed at a boundary area of the pixel region and at least one second common electrode between the first common electrodes;
• a second substrate;
• and
• a liquid crystal layer disposed between the first and second substrates,
• wherein the first common line, the second common electrode, the plurality of pixel electrodes and the auxiliary data line are formed of a same material and a same layer as one another and are disposed at a different level from the first common electrodes, and wherein a distance between the first common line and the auxiliary data line is greater than a distance between one of the first common electrode and the auxiliary data line.