Decoder architecture with sub-thermometer codes for DACs

A digital-to-analog converter (DAC) for converting a digital signal to an analog signal, the DAC comprising:

• a first thermometer decoder receiving the digital signal, the first thermometer decoder being configured to decode most-significant bits (MSBs) of the digital signal to generate a first thermometer code, wherein the first thermometer decoder comprises a first plurality of outputs;
• a plurality of macro cells identical to each other, with each coupled to one of the first plurality of outputs;
• a second thermometer decoder for receiving the digital signal, the second thermometer decoder being configured to decode middle bits of the digital signal to generate a second thermometer code, wherein the second thermometer decoder comprises a second plurality of outputs;
• and
• a macro cell comprising:
• a first plurality of unit cells controlled by least-significant bits (LSBs) of the digital signal and providing currents in a binary style;
• and
• a second plurality of unit cells providing identical currents, wherein each of the second plurality of unit cells is coupled to one of the second plurality of outputs;
• wherein the first plurality of unit cells comprises an X1 unit cell, an X2 unit cell, and an X4 unit cell, and wherein the second plurality of unit cells are X8 unit cells.

A method of performing a digital-to-analog conversion (DAC), the method comprising:

• dividing a digital input signal into most-significant bits (MSBs), least-significant bits (LSBs), and middle bits;
• generating a first thermometer code from the MSBs;
• generating a first combined current from the first thermometer code;
• generating a second thermometer code from the middle bits;
• generating a second combined current from the second thermometer code;
• generating a third combined current from the LSBs using binary decoding;
• and
• combining the first combined current, the second combined current, and the third combined current;
• wherein the step of generating the third combined current from the LSBs comprises using the LSBs to control the state of a plurality of binary unit cells, wherein a number of the binary unit cells is equal to a number of the LSBs, and wherein the step of generating the second combined current and the step of generating the third combined current are performed using a same macro cell and the macro cell comprises an Xl unit cell, an X2 unit cell, an X4 unit cell, and a plurality of additional unit cells capable of providing a same number of current units, and wherein the Xl unit cell, the X2 unit cell, the X4 unit cell, and the plurality of additional unit cells are laid out in an array, with micro cells in each of the X2 unit cell, the X4 unit cell, and the plurality of additional unit cells laid out symmetrically relative to a center of the array.