Programmable signal routing

A clock multiplexer circuit for programmably routing clock signals, comprising:

• a first switching module, including a reference clock input port, a first reference clock output port, a second reference clock output port, a first switch, a second switch, and a switch control port, configured to have the reference clock input port connected to the first output port via the first switch, the reference clock input port connected to the second reference clock output port via the second switch, each switch being in either an open or closed state depending on a signal received at the control port, and the first switching module is part of a first power domain;
• a second switching module, including a reference clock input port, a first reference clock output port, a second reference clock output port, a first switch, a second switch, and a switch control port, configured to have the reference clock input port connected to the first output port via the first switch, the reference clock input port connected to the second reference clock output port via the second switch, each switch being in either an open or closed state depending on a signal received at the control port, and the first switching module is part of a second power domain;
• and
• a first aggregator module, including a first input port, a second input port, an output port, and circuitry to output a single signal from among the signals received at the input ports, configured to have the first input port coupled with the first output port of the first switching module, and the second input port coupled with the first output port of the second switching module;
• and
• a second aggregator module, including a first input port, a second input port, an output port, and circuitry to output a single signal from among the signals received at the input ports, configured to have the first input port coupled with the second output port of the first switching module, and the second input port coupled with the second output port of the second switching module.

A programmable clock routing circuit on an integrated circuit chip, comprising:

• a first signal multiplexer, including a reference clock input port, at least three output ports, at least three switches, and a control logic input, the first signal multiplexer part of a first isolated power domain, the input port coupled with each output port via a switch, each switch being opened or closed according to signals received via the control port;
• a second signal multiplexer, including a reference clock input port, at least three output ports, at least three switches, and a control logic input, the second signal multiplexer part of a second isolated power domain, the input port coupled with each output port via a switch, each switch being opened or closed according to signals received via the control port;
• a first signal aggregator, including a first input port, at least a second input port, an output port, and circuitry to combine signals received on the input ports to one output signal on the output port, the first signal aggregator configured to have the first input port coupled with the first output port of the first signal multiplexer and to have the second input port coupled with the first output port of the second signal multiplexer, and the first signal aggregator is part of a third power domain;
• a second signal aggregator, including a first input port, at least a second input port, an output port, and circuitry to combine signals received on the input ports to one output signal on the output port, the second signal aggregator configured to have the first input port coupled with the first output port of the second signal multiplexer and to have the second input port coupled with the first output port of the first signal multiplexer, and the second signal aggregator is part of a third power domain;
• a first phase-locked loop module, including an input port, an output port, and circuitry to increase the frequency of a signal received on the input port and output a signal of increased frequency on the output port, the first phase-locked loop module configured to have the input port coupled with the output of the first signal aggregator and to be part of a fourth power domain;
• a second phase-locked loop module, including an input port, an output port, and circuitry to increase the frequency of a signal received on the input port and output a signal of increased frequency on the output port, the second phase-locked loop module configured to have the input port coupled with the output of the second signal aggregator and to be part of a fifth power domain;
• a first switching module, including an input port, a first output port, a second output port, a first switch, a second switch, and a control port, configured to have the input port connect to the first output port through the first switch, the input port connect to the second output port through the second switch, the state of each switch controlled by information received via the control port, and the input port coupled to the output port of the first phase-locked loop module, the third switching module part of the fourth power domain;
• a second switching module, including an input port, a first output port, a second output port, a first switch, a second switch, and a control port, configured to have the input port connect to the first output port through the first switch, the input port connect to the second output port through the second switch, the state of each switch controlled by information received via the control port, and the input port coupled to the output port of the second phase-locked loop module, the fourth switching module part of the fifth power domain;
• a third signal aggregator, including a first input port, at least a second input port, an output port, and circuitry to combine signals received on the input ports to one output signal on the output port, the third signal aggregator configured to have the first input port coupled with the first output port of the first switching module and to have the second input port coupled with the first output port of the second switching module, and the third signal aggregator is part of the third power domain;
• and
• a fourth signal aggregator, including a first input port, at least a second input port, an output port, and circuitry to combine signals received on the input ports to one output signal on the output port, the fourth signal aggregator configured to have the first input port coupled with the second output port of the second switching module and to have the second input port coupled with the second output port of the first switching module, and the fourth signal aggregator is part of the third power domain.