Clock generator, pulse generator utilizing the clock generator, and methods thereof

A clock generator for generating a first target clock signal, comprising:

• a multiphase controller, for receiving a reference clock signal to generate a frequency divided reference clock signal, and for generating a selecting signal;
• a control circuit, receiving the frequency divided reference clock signal, and for generating a plurality of candidate clock enable signals and a plurality of candidate delay selecting signals according to the frequency divided reference clock signal;
• at least one selector, for respectively selecting one of the candidate clock enable signals as an output clock enable signal and one of the candidate delay selecting signals as an output delay selecting signal according to the selecting signal;
• at least one register, for respectively registering the output clock enable signal and the output delay selecting signal as a first clock enable signal and a first delay selecting signal;
• and
• a first clock gating delay module, for receiving the reference clock signal, the first clock enable signal and the first delay selecting signal, and for passing the reference clock signal according to the first clock enable signal, to generate a first clock gated signal, and for delaying the first clock gated signal according to the first delay selecting signal to generate the first target clock signal.

A clock generating method for generating a first target clock signal, comprising:

• generating a first clock enable signal and a first delay selecting signal according to a reference clock signal;
• blocking the reference clock signal;
• passing the reference clock signal according to the first clock enable signal, to generate a first clock gated signal;
• and
• delaying the first clock gated signal according to the first delay selecting signal to generate the first target clock signal.