Dynamic clock feedback latch
AssigneeVIA Technologies, Inc.
InventorJohn L. Duncan
Life of this patent
Estimating the term…
Abstract
A dynamic clock feedback latch includes a feedback path that generates a data value on an output as a function of data inputs in response to a clock input going low and generates a latching value on the output after a delay from the clock input going high. A first transistor pre-charges a node high while the clock input is low. A second transistor provides a drain path for draining the node low from the pre-charged value while the clock input is high. The output controls a third transistor during the delay to drain the node to a low value if the data value is high and to retain the high value if the data value is low. The feedback path generates the predetermined latching value on the output after the delay to cause an inverted value of the data value to be latched onto the node.
Claims24
A dynamic clock feedback latch, comprising:
- a feedback path, configured to receive a clock input and one or more data inputs, and configured to generate a data value on an output as a function of the one or more data inputs in response to the clock input going low, and configured to generate a predetermined latching value on the output after a delay from the clock input going high;
- a first transistor, configured to provide a charge path from a charging source to a node to pre-charge the node to a high value while the clock input is low and to not provide the charge path while the clock input is high;
- a second transistor, configured to provide a drain path for selectively draining the node from the pre-charged high value to a low value while the clock input is high and to not provide the drain path while the clock input is low;
- a third transistor, coupled between the node and the second transistor and controlled by the output of the feedback path during the delay to drain the node to a low value through the second transistor drain path if the data value is high and to retain the node to the pre-charged high value if the data value is low;
- wherein the feedback path generates the predetermined latching value on the output after the delay from the clock input going high to cause to be latched onto the node an inverted value of the data value that was generated on the output as a function of the one or more data inputs.
A method for latching a data value in a dynamic clocked feedback manner, the method comprising:
- pre-charging a node to a high value while a clock input is low;
- generating a data value on an output as a function of one or more data inputs in response to the clock input going low;
- during an initial portion of the clock input being high, draining the node from the pre-charged high value to a low value if the data value is high and retaining the node to the pre-charged high value if the data value is low;
- and
- during a terminal portion of the clock input being high, generating a predetermined value on the output to cause the node to be isolated in order to latch onto the node either the low value or the high value in response to said draining or said retaining based on the data value during the initial portion of the clock input being high.
A computer program product for use with a computing device, the computer program product comprising:
- a computer usable storage medium, having computer readable program code embodied in said medium, for specifying a dynamic clock feedback latch, the computer readable program code comprising:
- first program code for specifying a feedback path, configured to receive a clock input and one or more data inputs, and configured to generate a data value on an output as a function of the one or more data inputs in response to the clock input going low, and configured to generate a predetermined latching value on the output after a delay from the clock input going high;
- second program code for specifying a first transistor, configured to provide a charge path from a charging source to a node to pre-charge the node to a high value while the clock input is low and to not provide the charge path while the clock input is high;
- third program code for specifying a second transistor, configured to provide a drain path for selectively draining the node from the pre-charged high value to a low value while the clock input is high and to not provide the drain path while the clock input is low;
- and
- fourth program code for specifying a third transistor, coupled between the node and the second transistor and controlled by the output of the feedback path during the delay to drain the node to a low value through the second transistor drain path if the data value is high and to retain the node to the pre-charged high value if the data value is low;
- wherein the feedback path generates the predetermined latching value on the output after the delay from the clock input going high to cause to be latched onto the node an inverted value of the data value that was generated on the output as a function of the one or more data inputs.
Dependencies are inferred from the claim text.