Clock signal selection circuit

A clock signal selection circuit comprising:

• a first AND circuit outputting a logical product signal of a clock selection signal and a first control signal;
• a second AND circuit outputting a logical product signal of a logical inversion signal of the clock selection signal and a second control signal;
• a first flip-flop inputting either the logical product signal that the first AND circuit outputs or a signal in accordance with the logical product signal and outputting a logical inversion signal of a first output signal in synchronization with a first clock signal to the second AND circuit as the second control signal;
• a first gated clock buffer inputting either the input signal to the first flip-flop or a signal in accordance with the input signal and gate-controlling the input signal by the first clock signal to output a third clock signal;
• a second flip-flop inputting either the logical product signal that the second AND circuit outputs or a signal in accordance with the logical product signal and outputting a logical inversion signal of a second output signal in synchronization with a second clock signal to the first AND circuit as the first control signal;
• a second gated clock buffer inputting either the input signal to the second flip-flop or a signal in accordance with the input signal and gate-controlling the input signal by the second clock signal to output a fourth clock signal;
• a first OR circuit outputting a logical sum signal of the third and fourth clock signals;
• and
• a clock stop setting circuit setting input signals to the first and second gated clock buffers to be a low level regardless of the clock selection signal when a clock stop signal is input.

A clock signal selection circuit comprising:

• a first AND circuit outputting a logical product signal of a clock selection signal and a first control signal;
• a second AND circuit outputting a logical product signal of a logical inversion signal of the clock selection signal and a second control signal;
• a first flip-flop inputting either the logical product signal that the first AND circuit outputs or a signal in accordance with the logical product signal and outputting a logical inversion signal of a first output signal in synchronization with a first clock signal to the second AND circuit as the second control signal;
• a first gated clock buffer inputting either the input signal to the first flip-flop or a signal in accordance with the input signal and gate-controlling the input signal by the first clock signal to output a third clock signal;
• a second flip-flop inputting either the logical product signal that the second AND circuit outputs or a signal in accordance with the logical product signal and outputting a logical inversion signal of a second output signal in synchronization with a second clock signal to the first AND circuit as the first control signal;
• a second gated clock buffer inputting either the input signal to the second flip-flop or a signal in accordance with the input signal and gate-controlling the input signal by the second clock signal to output a fourth clock signal;
• a first OR circuit outputting a logical sum signal of the third and fourth clock signals;
• and
• a switching prohibition circuit prohibiting output from switching from the second clock signal to the first clock signal when the first clock signal is stopped, and prohibiting output from switching from the first clock signal to the second clock signal when the second clock signal is stopped.

A clock signal selection circuit comprising:

• a first AND circuit outputting a logical product signal of a clock selection signal and a first control signal;
• a second AND circuit outputting a logical product signal of a logical inversion signal of the clock selection signal and a second control signal;
• a first flip-flop inputting either the logical product signal that the first AND circuit outputs or a signal in accordance with the logical product signal and outputting a logical inversion signal of a first output signal in synchronization with a first clock signal to the second AND circuit as the second control signal;
• a first gated clock buffer inputting either the input signal to the first flip-flop or a signal in accordance with the input signal and gate-controlling the input signal by the first clock signal to output a third clock signal;
• a second flip-flop inputting either the logical product signal that the second AND circuit outputs or a signal in accordance with the logical product signal and outputting a logical inversion signal of a second output signal in synchronization with a second clock signal to the first AND circuit as the first control signal;
• a second gated clock buffer inputting either the input signal to the second flip-flop or a signal in accordance with the input signal and gate-controlling the input signal by the second clock signal to output a fourth clock signal;
• a first OR circuit outputting a logical sum signal of the third and fourth clock signals;
• and
• a register writing input signals to the first and second gated clock buffers therein.