Synchronous phase detection circuit

Circuit of an electrothermal filter coupled to a phase detection circuit (50;

• 60;
• 70;
• 72;
• 74;
• 76;
• 78) arranged to function as a sigma-delta modulator, for determining a phase difference between a response signal (sv) of the electrothermal filter and a driving signal (sdr) of the electrothermal filter, the response signal and the driving signal having an equal frequency (f0;fdr), comprising:
• an electrothermal filter;
• a source input node (in) coupled to the electrothermal filter and configured to receive the response signal whose phase relationship with respect to the driving signal is to be determined;
• a feedback signal generator (58;
• 62) configured to provide a feedback signal (pfb), the feedback signal being generated with a frequency (f0) such that the feedback signal and the driving signal have the same frequency;
• a phase difference circuit (52) having a first signal input node coupled to the source input node (in) and a second signal input node coupled to the feedback signal generator (58;
• 62), and configured to receive the feedback signal,
• wherein the phase difference circuit is configured to determine an error signal (sum;
• mul;
• mulc;
• chm) that is a function of the phase difference between the response signal and the feedback signal and to provide the error signal at an output node;
• an integrator circuit (54) coupled to the output node of the phase difference circuit, configured to receive the error signal and configured to integrate the error signal to provide an integration signal (int);
• characterized by
• a digitizing circuit (56;
• 61) being provided with a sampling signal (fs) and coupled to the integration circuit, configured to receive the integration signal and configured to digitize the integration signal to provide a digitized integration signal (dv;
• bs);
• wherein the feedback signal generator (58;
• 62) is coupled to the digitizing circuit (56;
• 61);
• wherein the feedback signal generator is configured to provide the feedback signal based on the digitized integration signal from the digitizing circuit and to select the phase of the feedback signal from a plurality of fixed phases (ps1 . . . psn;p1, p2).