Multi-mode circuit and a method for preventing degradation in the multi-mode circuit

A method for minimizing degradation in a circuit having multiple operating modes, the method comprising:

• generating a first signal that inactivates a first transistor when the circuit enters into a second mode from a first mode, thereby minimizing degradation of the first transistor, the first transistor enabling functioning of the circuit in the first mode;
• and
• generating a second signal that activates a second transistor, when the circuit enters into the second mode from the first mode, which in turn inactivates a third transistor, thereby minimizing degradation of the third transistor, the third transistor enabling functioning of the circuit in the first mode and being subsequent to the first transistor
• wherein the first transistor and the third transistor are widely sized than the second transistor.

A NAND cell, comprising:

• first, second, and third nodes;
• a first PMOS transistor having a gate coupled to the first node and a drain coupled to the second node;
• a second PMOS transistor in parallel with the first PMOS transistor, and the second PMOS transistor having a gate coupled to the third node and a drain coupled to the second node;
• and
• first and second NMOS transistors in series with the first PMOS transistor,
• wherein the second NMOS transistor has a gate coupled to the third node and a drain coupled to a source of the first PMOS transistor, and the first NMOS transistor as a gate coupled to the first node and a drain coupled to the second node,
• and the NAND cell minimizes transistor degradation,
• wherein the first transistor and the third transistor are widely sized than the second transistor.