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US 8,013,633 B2Granted
Thin film transistor logic
AssigneeHewlett-Packard Development Company, L.P.
InventorsHao Luo, Ping Mei, Carl P. Taussig
Life of this patent
Estimating the term…
Abstract
A thin-film logic circuit, which can be fabricated entirely of TFTs of the same conductivity type, includes a logic stage connected to a supply voltage and a level shifter connected to a wider voltage range provided by the supply voltage and ground. The logic circuit produces output signals with full rail-to-rail signal range from ground to the supply voltage and can implement or include a basic logic component such as an inverter, a NAND gate, or a NOR gate or more complicated circuits in which many basic logic components are cascaded together. Such logic circuits can be fabricated directly on flexible structures or large areas such as in flat panel displays.
Claims16
A logic circuit comprising:
- a first level shifter comprising:
- a first NMOS transistor having a gate and drain coupled to a first supply voltage and a source coupled to a first node;
- and
- a second NMOS transistor coupled between the first node and a ground and having a gate to which a first input signal of the logic circuit is applied, the first supply voltage being higher than a high state of the first input signal and higher than a high state of an output signal from the logic circuit;
- a logic stage comprising:
- a third NMOS transistor coupled between a second supply voltage and a second node and having a gate coupled to the first node;
- and
- a fourth NMOS transistor coupled between the second node and the ground and having a gate to which the first input signal of the logic circuit is applied, wherein the output signal of the logic circuit is provided at the second node and the high state of the output signal corresponds to the second supply voltage;
- and
- a second level shifter comprising:
- a fifth NMOS transistor having a gate and a drain coupled to the first supply voltage and a source coupled to a third node;
- and
- a sixth NMOS transistor coupled between the third node and the ground and having a gate to which a second input signal of the logic circuit is applied, wherein
- the logic stage further comprises:
- a seventh NMOS transistor coupled between the second supply voltage and the second node and having a gate coupled to the third node;
- and
- an eighth NMOS transistor coupled between the second node and the ground and having a gate to which the second input signal of the logic circuit is applied.
14 more elements
A logic circuit comprising:
- a first set of NMOS transistors coupled between a first supply voltage and an output node at which an output signal of the logic circuit is produced;
- a set of level shifters coupled to a second supply voltage that is higher than the first supply voltage and coupled to receive respective input signals of the logic circuit, wherein each of the level shifters generates an internal signal that is applied to a gate of a corresponding one of the NMOS transistors in the first set, each of the internal signals has a high state that corresponds to the second supply voltage, and the second supply voltage is higher than a high state voltage of the input signals and higher than a high state voltage of the output signal;
- and
- a second set of NMOS transistors coupled between the output node and ground and having gates coupled to respectively receive the input signals, wherein
- each of the level shifters comprises:
- a first NMOS transistor having a gate and drain coupled to the second supply voltage and a source coupled to a first node;
- and
- a second NMOS transistor coupled between the first node and a ground and having a gate to which a first input signal of the logic circuit is applied.
5 more elements
A logic circuit comprising:
- a first set of NMOS transistors coupled between a first supply voltage and an output node at which an output signal of the logic circuit is produced;
- a set of level shifters coupled to a second supply voltage that is higher than the first supply voltage and coupled to receive respective input signals of the logic circuit, wherein each of the level shifters generates an internal signal that is applied to a gate of a corresponding one of the NMOS transistors in the first set, each of the internal signals has a high state that corresponds to the second supply voltage, and the second supply voltage is higher than a high state voltage of the input signals and higher than a high state voltage of the output signal;
- and
- a second set of NMOS transistors coupled between the output node and ground and having gates coupled to respectively receive the input signals, wherein
- the logic circuit is part of a decoder for a TFT array and is fabricated in a thin film with the TFT array.
2 more elements
A logic circuit comprising:
- a first level shifter connected to operate using a first supply voltage, receive a first input signal representing a first binary value, and produce at a first node a first internal signal representing the first binary value, wherein a high state of the first input signal is at a level of a second supply voltage and a high state of the first internal signal is at a level of the first supply voltage, the level of the first supply voltage being higher than the level of the second supply voltage;
- a second level shifter connected to operate using the first supply voltage, receive a second input signal representing a second binary value, and produce at a second node a second internal signal representing the second binary value, wherein a high state of the second input signal is at the level of the second supply voltage and a high state of the second internal signal is at the level of the first supply voltage;
- and
- a logic stage connected to the first node, the second node, and the second supply voltage, wherein the logic stage produces an output signal representing a binary value that depends on the first and second binary values, the output signal having a high state at the level of the second supply voltage, wherein
- the first level shifter comprises:
- a first NMOS transistor having a gate and drain coupled to a first supply voltage and a source coupled to the first node;
- and
- a second NMOS transistor coupled between the first node and a ground and having a gate to which a first input signal is applied.
5 more elements
Dependencies are inferred from the claim text.