Method and system for scaling channel length
AssigneeNational Semiconductor Corporation
InventorsLi-Heng Chou, Jiankang Bu
Life of this patent
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Abstract
A method for scaling channel length in a semiconductor device is provided. The method includes increasing a pitch to reduce a development inspection critical dimension (DICD) for a plurality of polysilicon lines. The polysilicon lines are trimmed to provide a reduced-size channel length, based on the reduced DICD, for each polysilicon line. For a particular embodiment, the semiconductor device is fabricated using a photolithography tool having a wavelength of 248 nm, the pitch is about 800 nm, and the reduced-size channel length is about 0.11 μm.
Claims20
A method for scaling channel length in a semiconductor device, comprising:
- increasing a pitch to reduce a development inspection critical dimension (DICD) for a plurality of polysilicon lines;
- and
- trimming the polysilicon lines to provide a reduced-size channel length, based on the reduced DICD, for each polysilicon line.
A semiconductor wafer, comprising:
- a plurality of polysilicon lines spaced apart by an increased-size pitch, the increased-size pitch reducing a development inspection critical dimension (DICD):
- and
- a trench formed in a drain region between each pair of adjacent polysilicon lines.
A method for aligning a drain contact in a semiconductor device having a scaled channel length, comprising:
- etching a trench in a substrate;
- forming a drain layer over the substrate, the drain layer comprising silicon;
- depositing an oxide in the trench to form a shallow trench isolation (STI) having a top surface that is higher than a surface of the drain layer by a step size;
- and
- depositing a first oxide layer outwardly of the drain layer and the STI, the first oxide layer having a thickness less than the step size.
Dependencies are inferred from the claim text.