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US 8,013,398 B2Granted
Semiconductor device
AssigneeKabushiki Kaisha Toshiba
InventorsShinji Mori, Tsutomu Sato, Koji Matsuo
Life of this patent
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Abstract
A semiconductor device includes a first pMISFET region having an Si channel, a second pMISFET region having an Si channel and an nMISFET region having an Si channel. First SiGe layers which apply first compression strain to the Si channel are embedded and formed in the first pMISFET region to sandwich the Si channel thereof and second SiGe layers which apply second compression strain different from the first compression strain to the Si channel are embedded and formed in the second pMISFET region to sandwich the Si channel thereof.
Claims5
A semiconductor device comprising:
- a semiconductor substrate,
- a first pMISFET formed on the semiconductor substrate and having a first Si channel formed on a surface of the semiconductor substrate, and first SiGe layers, which apply first compression strain to the first Si channel, embedded in the surface of the semiconductor substrate to sandwich the first Si channel,
- a second pMISFET formed on the semiconductor substrate to be electrically isolated from the first pMISFET and having a second Si channel formed on a surface of the semiconductor substrate, and second SiGe layers, which apply second compression strain different from the first compression strain to the second Si channel, embedded in the surface of the semiconductor substrate to sandwich the second Si channel, and
- an nMISFET formed on the semiconductor substrate to be electrically isolated from the first pMISFET and the second pMISFET and having a third Si channel formed on a surface of the semiconductor substrate.
1 more element
Dependencies are inferred from the claim text.