Back to results
US 8,013,397 B2Granted
Embedded stressed nitride liners for CMOS performance improvement
AssigneeInternational Business Machines Corporation
InventorsDureseti Chidambarrao, Omer H. Dokumaci
Life of this patent
Estimating the term…
Abstract
The present invention provides a semiconducting device including a gate region positioned on a mesa portion of a substrate; and a nitride liner positioned on the gate region and recessed surfaces of the substrate adjacent to the gate region, the nitride liner providing a stress to a device channel underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 275 MPa to about 450 MPa.
Claims18
A structure comprising:
- a semiconductor substrate having a mesa portion and recessed surfaces, wherein said mesa portion contains a mesa top surface and mesa sidewalls located above and adjoined to said recessed surfaces, and wherein said mesa top surface is vertically offset from said recessed surfaces;
- a single gated transistor comprising a gate region including a gate dielectric and a gate electrode, wherein said gate dielectric abuts said mesa top surface and is disjoined from said recessed surfaces and said mesa sidewalls;
- sidewall spacers abutting said mesa top surface, wherein outer sidewalls of said sidewall spacers contiguously extend vertically from said mesa sidewalls to a top portion of said sidewall spacers without a horizontal surface below a topmost surface of said gate electrode and are aligned to said mesa sidewalls;
- source and drain regions located under and aligned to said recessed surfaces, wherein a boundary of said source region is substantially aligned to an outer sidewall of said sidewall spacers in a vertical direction, and a boundary of said drain region is substantially vertically aligned to another outer sidewall of said sidewall spacers in said vertical direction;
- a nitride liner abutting said sidewall spacers, said mesa sidewalls, and said recessed surfaces and not abutting said mesa top surface, wherein said nitride liner provides a longitudinal stress to a device channel underlying said gate region in said mesa portion of said semiconductor substrate;
- and
- source and drain extension regions located under and aligned to said mesa portion and extending beneath said sidewall spacers, wherein a bottommost planar surface of said source extension region and a bottommost planar surface of said drain extension region are located below a horizontal plane including said recessed surfaces.
4 more elements
A structure comprising:
- a semiconductor substrate having a mesa portion and recessed surfaces, wherein said mesa portion contains a mesa top surface and mesa sidewalls located above and adjoined to said recessed surfaces, and wherein said mesa top surface is vertically offset from said recessed surfaces;
- a single gated transistor comprising a gate region including a gate dielectric and a gate electrode, wherein said gate dielectric abuts said mesa top surface and is disjoined from said recessed surfaces and said mesa sidewalls;
- sidewall spacers abutting said mesa top surface, wherein outer sidewalls of said sidewall spacers contiguously extend vertically from said mesa sidewalls to a top portion of said sidewall spacers without a horizontal surface below a topmost surface of said gate electrode and are aligned to said mesa sidewalls;
- source and drain regions located under and aligned to said recessed surfaces and substantially aligned to said sidewall spacers;
- source and drain extension regions located under and aligned to said mesa portion and extending beneath said sidewall spacers, wherein a bottommost planar surface of said source extension region and a bottommost planar surface of said drain extension region are located below a horizontal plane including said recessed surfaces;
- and
- a nitride liner abutting said sidewall spacers, said mesa sidewalls, and said recessed surfaces and not abutting said mesa top surface, wherein said nitride liner provides a longitudinal stress to a device channel underlying said gate region in said mesa portion of said semiconductor substrate.
4 more elements
Dependencies are inferred from the claim text.