US 8,013,395 B2Granted

Semiconductor device and method for fabricating the same

AssigneePanasonic Corporation

InventorNaoki Kotani

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Abstract

The distance between a substrate contact portion and an active region in a p-type MIS transistor is greater than the distance between a substrate contact portion and an active region in an n-type MIS transistor. Alternatively, the length of a protruding part of a gate electrode of the p-type MIS transistor that protrudes from the p-type MIS transistor's active region toward the p-type MIS transistor's substrate contact portion is shorter than the length of a protruding part of a gate electrode of the n-type MIS transistor that protrudes from the n-type MIS transistor's active region toward the n-type MIS transistor's substrate contact portion. Alternatively, a part of the p-type MIS transistor's substrate contact portion that is located opposite the p-type MIS transistor's gate electrode has a lower impurity concentration than the other part thereof. Alternatively, a protective film is formed only on the protruding part of the p-type MIS transistor's gate electrode that protrudes from the p-type MIS transistor's active region toward the p-type MIS transistor's substrate contact portion.

Claims18

Dependent claims

A semiconductor device having a dual-gate structure, the device comprising:

a first active region of an n-type MIS transistor and a second active region of a p-type MIS transistor formed on a semiconductor substrate so as to be adjacent to each other with a first isolation region interposed therebetween;
a first substrate contact portion of the n-type MIS transistor formed on the semiconductor substrate near the first active region;
a second substrate contact portion of the p-type MIS transistor formed on the semiconductor substrate near the second active region;
an n-type gate electrode formed over the first active region and containing an n-type impurity introduced thereinto;
a first p-type doped layer formed in the first substrate contact portion and containing a p-type impurity introduced thereinto;
a p-type gate electrode formed over the second active region and containing a p-type impurity introduced thereinto;
a first n-type doped layer formed in the second substrate contact portion and containing an n-type impurity introduced thereinto;
a second p-type doped layer formed in a protruding part of the n-type gate electrode, where the n-type gate electrode protrudes from the first active region toward the first substrate contact portion and containing a p-type impurity introduced thereinto;
and
a second n-type doped layer formed in a protruding part of the p-type gate electrode, where the p-type gate electrode protrudes from the second active region toward the second substrate contact portion and containing a n-type impurity introduced thereinto,
wherein the first active region and the first substrate contact portion are separated by a second isolation region located between the first active region and the first substrate contact portion,
the second active region and the second substrate contact portion are separated by a third isolation region located between the second active region and the second substrate contact portion,
a distance between the second substrate contact portion and the second active region is greater than a distance between the first substrate contact portion and the first active region, and
a width of the second n-type doped layer in the gate width direction is smaller than a width of the second p-type doped layer in the gate width direction.

11 more elements

A semiconductor device having a dual-gate structure, the device comprising:

a first active region of an n-type MIS transistor and a second active region of a p-type MIS transistor formed on a semiconductor substrate so as to be adjacent to each other with a first isolation region interposed therebetween;
a first substrate contact portion of the n-type MIS transistor formed on the semiconductor substrate near the first active region;
a second substrate contact portion of the p-type MIS transistor formed on the semiconductor substrate near the second active region;
an n-type gate electrode formed over the first active region and containing an n-type impurity introduced thereinto;
a p-type doped layer formed in the first substrate contact portion and containing a p-type impurity introduced thereinto;
a p-type gate electrode formed over the second active region and containing a p-type impurity introduced thereinto;
an n-type doped layer formed in the second substrate contact portion and containing an n-type impurity introduced thereinto;
a second p-type doped layer formed in a protruding part of the n-type gate electrode, where the n-type gate electrode protrudes from the first active region toward the first substrate contact portion and containing a p-type impurity introduced thereinto;
and
a second n-type doped layer formed in a protruding part of the p-type gate electrode, where the p-type gate electrode protrudes from the second active region toward the second substrate contact portion and containing a n-type impurity introduced thereinto,
wherein the first active region and the first substrate contact portion are separated by a second isolation region located between the first active region and the first substrate contact portion,
the second active region and the second substrate contact portion are separated by a third isolation region located between the second active region and the second substrate contact portion,
the length of a protruding part of the p-type gate electrode in the gate width direction that protrudes from the second active region toward the second substrate contact portion on the third isolation region is shorter than the length of a protruding part of the n-type gate electrode in the gate width direction that protrudes from the first active region toward the first substrate contact portion on the second isolation region, and
a width of the second n-type doped layer in the gate width direction is smaller than a width of the second p-type doped layer in the gate width direction.

11 more elements

A semiconductor device having a dual-gate structure, the device comprising:

a first active region of an n-type MIS transistor and a second active region of a p-type MIS transistor formed on a semiconductor substrate so as to be adjacent to each other with a first isolation region interposed therebetween;
a first substrate contact portion of the n-type MIS transistor formed on the semiconductor substrate near the first active region;
a second substrate contact portion of the p-type MIS transistor formed on the semiconductor substrate near the second active region;
an n-type gate electrode formed over the first active region and containing an n-type impurity introduced thereinto;
a first p-type doped layer formed in the first substrate contact portion and containing a p-type impurity introduced thereinto;
a p-type gate electrode formed over the second active region and containing a p-type impurity introduced thereinto;
and
a first n-type doped layer formed in the second substrate contact portion and containing an n-type impurity introduced thereinto,
wherein the first active region and the first substrate contact portion are separated by a second isolation region located between the first active region and the first substrate contact portion,
the second active region and the second substrate contact portion are separated by a third isolation region located between the second active region and the second substrate contact portion,
a distance between the second substrate contact portion and the second active region is greater than a distance between the first substrate contact portion and the first active region,
a width of the first active region in the gate length direction is smaller than a width of the first substrate contact portion in the gate length direction, and
a width of the second active region in the gate length direction is smaller than a width of the second substrate contact portion in the gate length direction.

10 more elements

A semiconductor device having a dual-gate structure, the device comprising:

a first active region of an n-type MIS transistor and a second active region of a p-type MIS transistor formed on a semiconductor substrate so as to be adjacent to each other with a first isolation region interposed therebetween;
a first substrate contact portion of the n-type MIS transistor formed on the semiconductor substrate near the first active region;
a second substrate contact portion of the p-type MIS transistor formed on the semiconductor substrate near the second active region;
an n-type gate electrode formed over the first active region and containing an n-type impurity introduced thereinto;
a p-type doped layer formed in the first substrate contact portion and containing a p-type impurity introduced thereinto;
a p-type gate electrode formed over the second active region and containing a p-type impurity introduced thereinto;
and
an n-type doped layer formed in the second substrate contact portion and containing an n-type impurity introduced thereinto,
wherein the first active region and the first substrate contact portion are separated by a second isolation region located between the first active region and the first substrate contact portion,
the second active region and the second substrate contact portion are separated by a third isolation region located between the second active region and the second substrate contact portion,
the length of a protruding part of the p-type gate electrode in the gate width direction that protrudes from the second active region toward the second substrate contact portion on the third isolation region is shorter than the length of a protruding part of the n-type gate electrode in the gate width direction that protrudes from the first active region toward the first substrate contact portion on the second isolation region,
a width of the first active region in the gate length direction is smaller than a width of the first substrate contact portion in the gate length direction, and
a width of the second active region in the gate length direction is smaller than a width of the second substrate contact portion in the gate length direction.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/819,365Filed 27 Jun 2007
Priority: JP 2006-21932411 Aug 2006
Published: US 2008/0036013 A114 Feb 2008
Granted: 6 Sep 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10D 84/85
Of only insulated-gate FETs [IGFET]: complementary IGFETs, e.g. CMOS
H10D 84/0177
Manufacturing their gate conductors: the gate conductors having different materials or different implants
H10D 84/0186
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their interconnections or electrodes, e.g. source or drain electrodes
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe