Method for manufacturing a high integration density power MOS device
AssigneeSTMicroelectronics S.r.l.
InventorsGiuseppe Arena, Giuseppe Ferla, Marco Camalleri
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AssigneeSTMicroelectronics S.r.l.
InventorsGiuseppe Arena, Giuseppe Ferla, Marco Camalleri
Estimating the term…
A process for the realization of a high integration density power MOS device includes the following steps of: providing a doped semiconductor substrate with a first type of conductivity; forming, on the substrate, a semiconductor layer with lower conductivity; forming, on the semiconductor layer, a dielectric layer of thickness comprised between 3000 and 13000 A (Angstroms); depositing, on the dielectric layer, a hard mask layer; masking the hard mask layer by means of a masking layer; etching the hard mask layers and the underlying dielectric layer for defining a plurality of hard mask portions to protect said dielectric layer; removing the masking layer; isotropically and laterally etching said dielectric layer forming lateral cavities in said dielectric layer below said hard mask portions; forming a gate oxide of thickness comprised between 150 and 1500 A (Angstroms) depositing a conductor material in said cavities and above the same to form a recess spacer, which is totally aligned with a gate structure comprising said thick dielectric layer and said gate oxide.
A high integration density power MOS device comprising a substrate of a doped semiconductor with a first type of conductivity whereon a semiconductor layer with lower conductivity is formed, transistor elementary structures Ti comprising body regions, arranged above in said semiconductor inside which the source regions are confined, characterised in that it comprises in each of said transistor elementary structures Ti a gate structure of the type with double thickness comprising a first thin layer of gate oxide onto which, at least partially, a dielectric layer is overlapped having thickness greater than said first layer and laterally delimited by lateral portions of conductive material, said gate structure further comprising a nitride upper portion above the thick dielectric layer and said lateral portions of conductor material.
A power MOS device, comprising:
An electronic system, comprising:
Dependencies are inferred from the claim text.