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US 8,013,370 B2Granted
Solid-state imaging device
AssigneeFujitsu Semiconductor Limited
InventorsHiroshi Kobayashi, Katsuyoshi Yamamoto, Tadao Inoue, Toshitaka Mizuguchi
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Abstract
A solid-state imaging device has a substrate in which are formed a pixel array portion having a plurality of pixels, and a peripheral circuitry portion. The device is characterized in that a first multilevel metallization structure is formed over the peripheral circuitry portion, and a second multilevel metallization structure thinner than the first multilevel metallization structure is formed over the pixel array portion.
Claims19
A solid-state imaging device comprising:
- a substrate in which are formed a pixel array portion having a plurality of pixels each of which includes a photo-electric converter and a transistor, and a peripheral circuitry portion peripheral to the pixel array portion;
- a first multilevel metallization structure including first multilevel connection layers, first multilevel dielectric layers therebetween, and first multilevel conductive vias formed in the first multilevel dielectric lavers for connecting the first multilevel connection layers to each other, and formed over the peripheral circuitry portion;
- and
- a second multilevel metallization structure including second multilevel connection layers, second multilevel dielectric layers therebetween, and second multilevel conductive vias formed in the second multilevel dielectric lavers for connecting the second multilevel connection lavers to each other, being thinner than the first multilevel metallization structure, and formed over the pixel array portion.
1 more element
A solid-state imaging device comprising:
- a substrate in which are formed a pixel array portion having a plurality of pixels each of which includes a photo-electric converter and a transistor, and a periphery circuitry portion peripheral to the pixel array portion;
- a first multilevel metallization structure which is formed over the peripheral circuitry portion and has a plurality of first connection layers, a plurality of first dielectric layers therebetween and a plurality of first vias for connecting the first connection layers to each other;
- and
- a second multilevel metallization structure which is formed over the pixel array portion and has a smaller number of second connection layers than the first multilevel metallization structure, a plurality of second connection layers therebetween and a plurality of second vias for connecting the second connection layers to each other.
1 more element
A solid-state imaging device comprising:
- a substrate in which are formed a pixel array portion having a plurality of pixels each of which includes a photo-electric converter and a transistor, and a periphery circuitry portion peripheral to the pixel array portion;
- a first multilevel metallization structure which is formed over the peripheral circuitry portion and has a plurality of first connection layers, a plurality of first dielectric layers therebetween and a plurality of first vias for connecting the first connection layers to each other;
- and
- a second multilevel metallization structure which is formed over the pixel array portion and has a smaller number of second connection layers than the first multilevel metallization structure, a plurality of second dielectric layers therebetween and a plurality of second vias for connecting the second connection layers to each other, over which a color filter film is formed at a level corresponding to the uppermost level of the first multilevel metallization structure.
1 more element
A solid-state imaging device comprising:
- a substrate in which are formed a pixel array portion having a plurality of pixels each of which includes a photo-electric converter and a transistor, and a peripheral circuitry portion peripheral to the pixel array portion;
- a first multilevel connection layers structure including first connection layers, first dielectric layers therebetween and first vias for connecting the first connection layers to each other, and formed over the peripheral circuitry portion;
- and
- a second multilevel connecting layers structure including second connection layers, second dielectric layers therebetween and second vias for connecting the second connection lavers to each other, and formed over the pixel array portion,
- wherein the thickness of the first dielectric layers of the first multilevel connection layers structure is thinner than the thickness of the second dielectric layers of the second multilevel connection layers structure.
2 more elements
Dependencies are inferred from the claim text.