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US 8,013,368 B2Granted
Replacement gates to enhance transistor strain
AssigneeIntel Corporation
InventorMark T. Bohr
Life of this patent
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Abstract
Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.
Claims5
An apparatus comprising:
- an NMOS transistor having a strained first channel on a substrate, wherein the NMOS transistor includes a p-well on the substrate, the strained first channel between n-doped regions in the p-well, and a first gate structure on the strained first channel, the first gate structure including a high-k gate dielectric, an n-type work function metal, and a gate electrode fill material that provides a tensile strain in the strained first channel, wherein the gate electrode fill material that provides the tensile strain comprises at least one of titanium, and titanium carbide;
- and
- a PMOS transistor having a strained second channel on the substrate, wherein the PMOS transistor includes an n-well on the substrate, and a second gate structure over the strained second channel.
Dependencies are inferred from the claim text.