CMOS image sensor configured to provide reduced leakage current

A complementary metal-oxide-semiconductor (CMOS) image sensor (CIS), comprising:

• a semiconductor substrate including a photodiode therein as a light sensing unit;
• a floating diffusion region of a first conductivity type in the semiconductor substrate and configured to receive charges generated in the photodiode, the floating diffusion region comprising a first region of a second conductivity type at a surface thereof and a second region of the first conductivity type at the surface thereof adjacent the first region, wherein the second conductivity type is different from the first conductivity type;
• a power supply voltage region of the first conductivity type in the semiconductor substrate;
• a reset transistor comprising a reset gate electrode on a surface of the substrate and a channel region extending between the floating diffusion region and the power supply voltage region beneath the reset gate electrode such that the floating diffusion region and the power supply voltage regions define source/drain regions for the reset transistor, wherein a first portion of the channel region adjacent to the floating diffusion region comprises the second conductivity type and a second portion of the channel region adjacent to the power supply voltage region comprises the first conductivity type, and wherein the reset transistor is configured to discharge the charges stored in the floating diffusion region in response to a reset control signal;
• and
• a conductive layer on the second region of the floating diffusion region and configured to electrically connect the floating diffusion region to another device.

A complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) comprising:

• a semiconductor substrate including a photodiode therein as a light sensing unit;
• a floating diffusion region of a first conductivity type in the semiconductor substrate and configured to receive charges generated in the photodiode;
• a power supply voltage region of the first conductivity type in the semiconductor substrate;
• a reset transistor comprising a reset gate electrode on a surface of the substrate and a channel region extending between the floating diffusion region and the power supply voltage region beneath the reset gate electrode such that the floating diffusion region and the power supply voltage regions define source/drain regions for the reset transistor, wherein a first portion of the channel region adjacent to the floating diffusion region comprises a second conductivity type and a second portion of the channel region adjacent to the power supply voltage region comprises the first conductivity type, wherein the second conductivity type is different from the first conductivity type, and wherein the reset transistor is configured to discharge the charges stored in the floating diffusion region in response to a reset control signal;
• a device isolation layer on the substrate adjacent to the floating diffusion region;
• and
• an impurity region of the second conductivity type in the substrate separating the floating diffusion region from the device isolation layer.